公开(公告)号：US11227086B2

公开(公告)日：2022-01-18

申请号：US15931445

申请日：2020-05-13

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Thomas Boesch ,  Giuseppe Desoli

IPC: G02B6/35 ,  G06F30/327 ,  G06N20/10 ,  G06N3/04 ,  G06N3/08 ,  G06F30/34 ,  G06N20/00 ,  G06N7/00 ,  G06F115/08 ,  G06N3/063 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78

Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer, a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.

公开(公告)号：US20220004509A1

公开(公告)日：2022-01-06

申请号：US17479255

申请日：2021-09-20

Applicant: STMicroelectronics S.r.l. ,  Proton World International N.V.

Inventor： Olivier Van Nieuwenhuyze ,  Amedeo Veneroso

IPC: G06F13/16 ,  G06F12/0842 ,  G06F12/14

Abstract: An embedded electronic system includes a volatile memory and a processor configured to execute a low-level operating system that manages allocation of areas of the volatile memory to a plurality of high-level operating systems. Each high-level operating system executes one or more applications. The system is configured so that execution data of one or a plurality of tasks of a first application are partly transferred, by the low-level operating system, from the volatile memory to a non-volatile memory when the execution of the task of the first application is interrupted by the execution of a task of a second application. The system is also configured so that the applications of any one of the high-level operating systems do not have access to the areas of the volatile memory allocated to the applications of all the other high-level operating systems.

公开(公告)号：US20220003814A1

公开(公告)日：2022-01-06

申请号：US17479510

申请日：2021-09-20

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Giorgio MAIELLARO ,  Angelo SCUDERI ,  Angela BRUNO ,  Salvatore SCACCIANOCE

IPC: G01R31/28 ,  G01S7/40

Abstract: A radio-frequency receiver includes built-in-self-test (BIST) circuitry which generates a self-test signal. A local oscillator signal is divided. A self-test oscillation signal is generated, based, at least in part, on the frequency-divided local oscillation signal. The self-test signal is generated based on the self-test oscillation signal. The BIST circuitry includes a divider, which divides the self-test oscillation signal. The frequency-divided local oscillation signal and the divided self-test oscillation signal are used to perform one or more of generating the self-test oscillation signal and controlling the generation of the self-test oscillation signal. The radio-frequency receiver may be an automotive radar receiver.

公开(公告)号：US20210409914A1

公开(公告)日：2021-12-30

申请号：US17356180

申请日：2021-06-23

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS S.r.l.

Inventor： Karimuddin SAYED ,  Chandandeep Singh PABLA ,  Lorenzo BRACCO ,  Federico RIZZARDINI

IPC: H04W4/38 ,  H04W4/70 ,  G01D9/00 ,  G01D5/244

Abstract: In an embodiment, a device comprises a memory, which, in operation, stores data samples associated with a plurality of data sensors, and circuitry, coupled to the memory, wherein the circuitry, in operation, generates synchronized output data sets associated with the plurality of data sensors. Generating a synchronized output data set includes: determining a reference sample associated with a sensor of the plurality of sensors; verifying a timing validity of a data sample associated with another sensor of the plurality of sensors; identifying a closest-in-time data sample associated with the another sensor of the plurality of sensors with respect to the reference sample; and generating the synchronized output data set based on interpolation.

公开(公告)号：US20210405346A1

公开(公告)日：2021-12-30

申请号：US17355861

申请日：2021-06-23

Applicant: STMicroelectronics S.r.l.

Inventor： Domenico GIUSTI ,  Massimiliano MERLI

IPC: G02B26/04 ,  H01L41/053 ,  H01L41/083 ,  H01L41/09 ,  H01L41/277

Abstract: A MEMS actuator includes a main body having a central portion, couplable to a substrate, and a peripheral portion suspended over the substrate when the central portion is coupled to the substrate. The peripheral portion has a deformable structure extending around the central portion, and forming successively arranged membranes. The MEMS actuator includes bearing structures and corresponding piezoelectric actuators. The bearing structures are fixed at their top to the deformable structure and laterally delimit corresponding cavities, each having a lateral opening facing the central portion of the main body and closed at the top by a membrane. A fixed part of the membrane is fixed to the underlying bearing structure and a suspended part is laterally offset with respect to the underlying bearing structure. The piezoelectric actuators are controllable to cause deformation of the corresponding membrane and rotation of the bearing structures around the central portion of the main body.

公开(公告)号：US11212893B2

公开(公告)日：2021-12-28

申请号：US16885507

申请日：2020-05-28

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Difazio ,  Stefano Corradi ,  Giuseppe Calcagno

IPC: H05B45/34 ,  H03M1/78 ,  H05B45/345

Abstract: An apparatus includes a digital-to-analog converter coupled in series with a source follower, wherein the digital-to-analog converter is configured to control a current flowing through the source follower, and an amplifier having a first input coupled to a reference generator, a second input coupled to a common node of the source follower and the digital-to-analog converter, and an output coupled to a gate of the source follower.

公开(公告)号：US20210399156A1

公开(公告)日：2021-12-23

申请号：US17464299

申请日：2021-09-01

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Massimo Cataldo MAZZILLO ,  Giovanni CONDORELLI

IPC: H01L31/107 ,  H01L31/18 ,  G01N21/75 ,  H01L27/146

Abstract: A device for detecting a chemical species, including a Geiger-mode avalanche diode, which includes a body of semiconductor material delimited by a front surface. The semiconductor body includes: a cathode region having a first type of conductivity, which forms the front surface; and an anode region having a second type of conductivity, which extends in the cathode region starting from the front surface. The detection device further includes: a sensitive structure arranged on the anode region and including at least one sensitive region, which has an electrical permittivity that depends upon the concentration of the chemical species; and a resistive region, arranged on the sensitive structure and electrically coupled to the anode region.

公开(公告)号：US11205462B2

公开(公告)日：2021-12-21

申请号：US17010704

申请日：2020-09-02

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Vivek Tyagi ,  Vikas Rana ,  Chantal Auricchio ,  Laura Capecchi

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/22

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

公开(公告)号：US20210384852A1

公开(公告)日：2021-12-09

申请号：US17323602

申请日：2021-05-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH ,  STMicroelectronics (Alps) SAS

Inventor： Aldo Occhipinti ,  Christophe Roussel ,  Fritz Burkhardt ,  Ignazio Testoni

IPC: H02P7/03 ,  H02P7/29 ,  H03K3/037 ,  H03K17/687 ,  E05F15/60

Abstract: An embodiment driver circuit comprises a power supply pin configured to receive a power supply voltage, and a set of control pins configured to provide a set of control signals for controlling switching of a set of switches of an h-bridge circuit comprising a pair of high-side switches and a pair of low-side switches. The driver circuit comprises control circuitry coupled to the control pins and configured to generate the control signals, and sensing circuitry coupled to the power supply pin and configured to generate a detection signal indicative of the power supply voltage exceeding a threshold value. The control circuitry is sensitive to the detection signal and is configured to generate the control signals to activate one of the pair of high-side switches and the pair of low-side switches and de-activate the other of the pair of high-side switches and the pair of low-side switches.

公开(公告)号：US20210384830A1

公开(公告)日：2021-12-09

申请号：US17335523

申请日：2021-06-01

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro BERTOLINI ,  Alberto CATTANI ,  Alessandro GASPARINI

IPC: H02M3/158 ,  H02M1/00

Abstract: A control circuit for controlling switching operation of a switching stage of a converter includes a phase detector circuit that generates a pulse-width modulated (PWM) signal in response to a phase comparison of two clock signals. A first clock signal has a frequency determined as a function of a first feedback signal proportional to converter output voltage. A first transconductance amplifier generates a first current indicative of a difference between a reference voltage and the first feedback signal, and a second transconductance amplifier generates a second current indicative of a difference between the reference voltage and a second feedback signal proportional to a derivative of the converter output voltage. A delay line introduces a delay in the first clock signal that is dependent on the first and second currents as well as a compensation current dependent on a selected operational mode of the converter.