公开(公告)号：US06395609B1

公开(公告)日：2002-05-28

申请号：US09812095

申请日：2001-03-19

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21331

CPC classification number: H01L29/7311

Abstract: A MOSBJT (Metal Oxide Semiconductor Bipolar Junction Transistor) is formed to have both the higher current drive capability of the BJT and the smaller device area of the scaled down MOSFET. The MOSBJT includes a collector region and an emitter region comprised of a semiconductor material with a first type of dopant. A base region is disposed between the collector region and the emitter region, and the base region is comprised of a semiconductor material with a second type of dopant that is opposite of the first type of dopant. Unlike a conventional BJT, a base terminal of the MOSBJT is comprised of a dielectric structure disposed over the base region and comprised of a gate structure disposed over the dielectric structure. Unlike a conventional MOSFET, the dielectric structure of the MOSBJT is relatively thin such that a tunneling current through the dielectric structure results when a turn-on voltage is applied on the gate structure. This tunneling current is a base current of the MOSBJT. Furthermore, unlike a conventional MOSFET, the dielectric structure and the gate structure of the MOSBJT are not disposed over the collector region and the emitter region to prevent tunneling current between the gate structure and the collector and emitter regions.

Abstract translation: 形成MOSBJT（金属氧化物半导体双极结晶体管）以具有BJT的较高电流驱动能力和缩小的MOSFET的较小器件面积。 MOSBJT包括集电极区域和由具有第一类型掺杂剂的半导体材料组成的发射极区域。 基极区域设置在集电极区域和发射极区域之间，并且基极区域由具有与第一类型掺杂剂相反的第二类型掺杂剂的半导体材料构成。 与常规BJT不同，MOSBJT的基极端子由设置在基极区域上的电介质结构构成，并且包括设置在电介质结构上的栅极结构。 与常规MOSFET不同，MOSBJT的电介质结构相对较薄，使得当在栅极结构上施加导通电压时，导致通过电介质结构的隧穿电流。 该隧穿电流是MOSBJT的基极电流。 此外，与常规MOSFET不同，MOSBJT的电介质结构和栅极结构不会设置在集电极区域和发射极区域上，以防止栅极结构与集电极和发射极区域之间的隧穿电流。

公开(公告)号：US06391782B1

公开(公告)日：2002-05-21

申请号：US09597598

申请日：2000-06-20

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21311

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/42384 ,  H01L29/66795

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs. The MOSFETs can include a gate structure above active lines manufactured by utilizing a spacer structure as a mask. The spacer structure can be silicon dioxide formed in an etch back process. The gate structure can surround more than one side of the active line.

Abstract translation: 超大规模集成（ULSI）电路包括MOSFET。 MOSFET可以包括通过利用间隔结构作为掩模制造的有源线上的栅极结构。 间隔结构可以是在回蚀工艺中形成的二氧化硅。 栅极结构可以围绕有源线的多于一侧。

公开(公告)号：US06391753B1

公开(公告)日：2002-05-21

申请号：US09597624

申请日：2000-06-20

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L214763

CPC classification number: H01L21/0337 ,  H01L21/2815 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823437 ,  H01L21/823828 ,  H01L21/84

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs. The MOSFETs can include a gate structure manufactured by utilizing a spacer structure as a mask. The spacer structure can be silicon dioxide formed in an etch back process.

Abstract translation: 超大规模集成（ULSI）电路包括MOSFET。 MOSFET可以包括通过利用间隔结构作为掩模制造的栅极结构。 间隔结构可以是在回蚀工艺中形成的二氧化硅。

公开(公告)号：US06376320B1

公开(公告)日：2002-04-23

申请号：US09712995

申请日：2000-11-15

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66507 ,  H01L29/66545

Abstract: For fabricating a field effect transistor having a gate structure on a gate dielectric within an active device area of a semiconductor substrate, a hardmask dielectric material covers a top surface of the gate structure. A drain silicide is formed with a drain contact junction that is exposed, and a source silicide is formed with a source contact junction that is exposed. The drain silicide and the source silicide have a first thickness and are comprised of a first silicide material. The hardmask dielectric material that covers the top surface of the gate structure prevents formation of silicide with the gate structure during formation of the drain silicide and the source silicide. An encapsulating dielectric material is then deposited to cover the drain silicide and the source silicide using a low temperature of less than about 400° Celsius. The hardmask dielectric material is etched away from the top surface of the gate structure to expose the top surface of the gate structure. A gate silicide is formed with the gate structure, and the gate silicide has a second thickness and is comprised of a second silicide material. The encapsulating dielectric material covering the drain silicide and the source silicide prevents further formation of the drain silicide and the source silicide during formation of the gate silicide. The present invention may be used to particular advantage when the first thickness of the drain and source suicides is less than the second thickness of the gate silicide and when the first silicide material of the drain and source silicides is different from the second silicide material of the gate silicide.

Abstract translation: 为了制造在半导体衬底的有源器件区域内的栅极电介质上具有栅极结构的场效应晶体管，硬掩模电介质材料覆盖栅极结构的顶表面。 漏极硅化物形成有露出的漏极接触结，并且源极硅化物形成有暴露的源极接触结。 漏极硅化物和源硅化物具有第一厚度并且由第一硅化物材料构成。 覆盖栅极结构的顶表面的硬掩模电介质材料防止了在形成漏极硅化物和源极硅化物期间与栅极结构形成硅化物。 然后使用低于约400℃的低温沉积封装介电材料以覆盖漏极硅化物和源硅化物。 将硬掩模介电材料从栅极结构的顶表面蚀刻掉以露出栅极结构的顶表面。 栅极硅化物与栅极结构形成，并且栅极硅化物具有第二厚度并且由第二硅化物材料构成。 覆盖漏极硅化物和源硅化物的封装电介质材料防止在形成栅极硅化物期间进一步形成漏极硅化物和源极硅化物。 当漏极和源自身的第一厚度小于栅极硅化物的第二厚度时，并且当漏极和源极硅化物的第一硅化物材料不同于第二硅化物材料时，本发明可以被用于特别有利的 栅极硅化物。

公开(公告)号：US06365445B1

公开(公告)日：2002-04-02

申请号：US09846957

申请日：2001-05-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2184

CPC classification number: H01L29/66757 ,  H01L29/458 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78696

Abstract: For fabricating a field effect transistor on a buried insulating material in SOI (semiconductor on insulator) technology, a dielectric island is formed on the buried insulating material. An opening is etched through the buried insulating material at a location away from the dielectric island. An amorphous semiconductor material is deposited to fill the opening through the buried insulating material and to surround the dielectric island. The amorphous semiconductor material is polished until the top surface of the dielectric island is exposed and such that the amorphous semiconductor material surrounds the dielectric island. A layer of the amorphous semiconductor material is deposited on top of the dielectric island and on top of the amorphous semiconductor material surrounding the dielectric island. The amorphous semiconductor material surrounding the dielectric island and the layer of the amorphous semiconductor material are recrystallized to form a substantially single crystal structure of semiconductor material. A gate dielectric and a gate electrode of the field effect transistor are formed on top of a thinner portion of the semiconductor material disposed on the dielectric island. A drain extension region and a source extension region are formed by implanting a drain and source dopant into exposed regions of the thinner portion of the semiconductor material disposed on the dielectric island to minimize short channel effects. A drain contact region and a source contact region are formed from a thicker portion of the semiconductor material disposed to the sides of the dielectric island. The drain and source silicides are formed with the thicker drain and source contact regions to minimize parasitic resistance at the drain and source.

Abstract translation: 为了在SOI（绝缘体上半导体）技术的掩埋绝缘材料上制造场效应晶体管，在掩埋绝缘材料上形成介电岛。 在远离电介质岛的位置处通过掩埋绝缘材料蚀刻开口。 沉积非晶半导体材料以填充通过掩埋绝缘材料的开口并围绕电介质岛。 非晶半导体材料被抛光直到电介质岛的顶表面被暴露，并且非晶半导体材料围绕电介质岛。 非晶半导体材料的一层沉积在电介质岛的顶部上，并且在包围电介质岛的非晶半导体材料的顶部上。 围绕电介质岛的非晶半导体材料和非晶半导体材料层被重结晶以形成半导体材料的基本单晶结构。 场效应晶体管的栅极电介质和栅电极形成在设置在介质岛上的半导体材料的较薄部分的顶部。 通过将漏极和源极掺杂剂注入设置在介质岛上的半导体材料的较薄部分的暴露区域来形成漏极延伸区域和源延伸区域，以最小化短沟道效应。 漏极接触区域和源极接触区域由设置在电介岛的侧面的半导体材料的较厚部分形成。 漏极和源极硅化物形成有较厚的漏极和源极接触区域，以最小化漏极和源极处的寄生电阻。

公开(公告)号：US06342438B2

公开(公告)日：2002-01-29

申请号：US09187379

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L21265

CPC classification number: H01L21/823842 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823871

Abstract: A dual doped CMOS gate structure utilizes a nitrogen implant to suppress dopant inter-diffusion. The nitrogen implant is provided above standard trench isolation structures. Alternatively, an oxygen implant can be utilized. The use of the implant allows an increase in packing density for ultra-large-scale integrated (ULSI) circuits. The doping for N-channel and P-channel active regions can be completed when the polysilicon gate structures are doped.

Abstract translation: 双掺杂CMOS栅极结构利用氮注入来抑制掺杂剂相互扩散。 在标准沟槽隔离结构之上提供氮注入。 或者，可以使用氧注入。 使用植入物可以提高超大规模集成（ULSI）电路的封装密度。 当掺杂多晶硅栅极结构时，可以完成N沟道和P沟道有源区的掺杂。

公开(公告)号：US06284582B1

公开(公告)日：2001-09-04

申请号：US09398246

申请日：1999-09-17

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L218238

CPC classification number: H01L29/0895 ,  H01L27/0722 ,  H01L29/735

Abstract: A method of forming a metal oxide semiconductor (MOS)-controlled bipolar transistor includes tilt angle implanting a first impurity into a semiconductor substrate and implanting a second impurity into the semiconductor substrate to form an emitter and a collector. A corresponding transistor arranged as to combine the large current drive capacity of a bipolar junction transistor (BJT) with the smaller device size of a metal oxide semiconductor field effect transistor (MOSFET) is also provided. The transistor includes a semiconductor structure, a gate located proximate the semiconductor structure, a gate insulator disposed intermediate the semiconductor structure and the gate, a source region located in the semiconductor structure, a drain region located in the semiconductor structure, and a buffer region located in the semiconductor structure proximate the drain region.

Abstract translation: 形成金属氧化物半导体（MOS）控制的双极晶体管的方法包括将第一杂质注入到半导体衬底中并将第二杂质注入到半导体衬底中以形成发射极和集电极的倾斜角。 还提供了将双极结型晶体管（BJT）的大电流驱动能力与金属氧化物半导体场效应晶体管（MOSFET）的较小器件尺寸组合的相应晶体管。 晶体管包括半导体结构，位于半导体结构附近的栅极，设置在半导体结构和栅极之间的栅极绝缘体，位于半导体结构中的源极区域，位于半导体结构中的漏极区域和位于半导体结构中的缓冲区域 在靠近漏极区域的半导体结构中。

公开(公告)号：US06265293B1

公开(公告)日：2001-07-24

申请号：US09384121

申请日：1999-08-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21425

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/7833

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region is between 10-15 nm below the top surface of the substrate, and the deep amorphous region is between 150-200 nm below the top surface of the substrate. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs). A step separate from the annealing step for the source/drain regions is utilized for annealing the gate conductor.

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法采用双非晶化技术。 该技术产生了300nm厚的浅非晶区和深非晶区。 浅非晶区域在衬底的顶表面之下10-15nm之间，深非晶区域在衬底顶表面之下的150-200nm之间。 该过程可用于P沟道或N沟道金属氧化物半导体场效应晶体管（MOSFET）。 与源极/漏极区域的退火步骤分离的步骤用于退火栅极导体。

公开(公告)号：US06265291B1

公开(公告)日：2001-07-24

申请号：US09224754

申请日：1999-01-04

Applicant: Bin Yu ,  Emi Ishida

Inventor： Bin Yu ,  Emi Ishida

IPC: H01L2104

CPC classification number: H01L21/28518 ,  H01L21/26506

Abstract: A method of manufacturing an integrated circuit to optimize the contact resistance between impurity diffusing layers and silicide is disclosed herein. The method includes implanting a first material to a layer of semiconductor to create a buried amorphous silicon layer; implanting a second material in the layer of semiconductor and buried amorphous layer, forming a dopant profile region with a curved shape; depositing a layer of metal on the layer of semiconductor; melting the buried amorphous layer to reconfigure the curved shape to a substantially vertical profile of maximum dopant concentration; and forming silicide with the layer of semiconductor and layer of metal, the bottom of the silicide located in the vertical shape on the dopant profile region.

Abstract translation: 本文公开了制造用于优化杂质扩散层和硅化物之间的接触电阻的集成电路的方法。 该方法包括将第一材料注入到半导体层中以产生埋入的非晶硅层; 将第二材料注入到半导体层和埋入非晶层中，形成具有弯曲形状的掺杂剂分布区域; 在半导体层上沉积金属层; 熔化埋入的非晶层以将弯曲形状重新配置为最大掺杂剂浓度的基本垂直分布; 并且用半导体层和金属层形成硅化物，硅化物的底部位于掺杂物分布区域上的垂直形状。

公开(公告)号：US06265256B1

公开(公告)日：2001-07-24

申请号：US09156238

申请日：1998-09-17

Applicant: Judy Xilin An ,  Bin Yu ,  Yowjuang W. Liu

Inventor： Judy Xilin An ,  Bin Yu ,  Yowjuang W. Liu

IPC: H01L218238

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L21/823468 ,  H01L29/6659

Abstract: A method for making a ULSI MOSFET includes establishing a gate void in a field oxide layer above a silicon substrate, after source and drain regions with associated source and drain extensions have been established in the substrate. A gate electrode is deposited in the void and gate spacers are likewise deposited in the void on the sides of the gate electrode, such that the gate electrode is spaced from the walls of the void. The spacers, not the gate electrode, are located above the source/drain extensions, such that fringe coupling between the gate electrode and the source and drain extensions is suppressed.

Abstract translation: 制造ULSI MOSFET的方法包括：在衬底中建立具有相关源极和漏极延伸部分的源极和漏极区域之后，在硅衬底上的场氧化物层中建立栅极空隙。 栅电极沉积在空隙中，并且栅极间隔物同样沉积在栅电极的侧面上的空隙中，使得栅电极与空隙的壁间隔开。 间隔件而不是栅电极位于源极/漏极延伸部上方，从而抑制栅极电极和源极和漏极延伸部之间的边缘耦合。