Abstract:
An output buffer is disclosed. The output buffer includes an input-stage circuit, an output-stage circuit and a compensation circuit. The compensation circuit includes a capacitor, a first switch, a second switch, a third switch, and a fourth switch. The input-stage circuit receives a differential input signal and outputting a response signal. The output-stage circuit receives the response signal and outputting an output signal. The first switch controls a connection between the input-stage circuit and a first terminal of the capacitor. The second switch controls the connection between an output terminal of the compensation circuit and a second terminal of the capacitor. The third switch controls the connection between the input-stage circuit and the second-terminal of the capacitor. The forth switch controls the connection between the output terminal of the compensation circuit and the first terminal of the capacitor.
Abstract:
A coordinate calculating method includes acquiring a plurality of first end capacitances and a plurality of second end capacitances corresponding to a plurality of sensing channels of a single-layer capacitive touch device. Differences between the plurality of first end capacitances and a plurality of first baselines are calculated for acquiring a plurality of first differences and calculating differences between the plurality of second end capacitances and a plurality of second baselines for acquiring a plurality of second differences The first difference and the second difference of each sensing channel are added for acquiring a plurality of total capacitances. Whether the single-layer capacitive touch device is pressed is determined according to the plurality of total capacitances and a threshold. A coordinate of at least one touch point is outputted when determining the single-layer capacitive touch device is pressed.
Abstract:
An integrated circuit (IC) including a high-speed signal input pin, a common node, a high-speed signal output pin, and a core circuit is provided. The high-speed signal input pin and the high-speed signal output pin are disposed on a package of the IC. The common node and the core circuit are disposed in the IC. The common node is directly and electrically coupled to the high-speed signal input pin. The high-speed signal output pin is directly and electrically coupled to the common node. A high-speed signal input terminal of the core circuit is directly and electrically coupled to the common node.
Abstract:
An image processing unit including an always on circuit block and a non-always on circuit block is provided. When operating under a first operation mode, the non-always on circuit block receives a bias voltage from a power supply unit, so as to perform an image processing operation on an image input signal. When operating under a second operation mode, the non-always on circuit block stops receiving the bias voltage from the power supply unit, so as to stop the image processing operation, and at least a microcontroller of the non-always on circuit block is powered down. One of the always on circuit block and the non-always on circuit block controls the power supply unit to stop supplying the bias voltage to the non-always on circuit block according an event trigger signal, such that the non-always on circuit block enters the second operation mode from the first operation mode.
Abstract:
A noise estimation apparatus for calculating a noise estimation value of a frame of an image is provided. The noise estimation apparatus includes a distribution calculation unit, a variance calculation unit, a distribution curve generation module and a noise estimation unit. The distribution calculation unit generates a pixel distribution according to multiple pixel data of an ith block of the frame and multiple previous pixel data of the ith block of a previous frame. The variance calculation unit combines the pixel data and the previous pixel data to generate a variance value. The curve distribution generation module generates a curve distribution according to the variance value, and compares the pixel distribution with the curve distribution to generate a weighting value. The noise estimation unit outputs the noise estimation value according to the weighting value and the variance value corresponding to each of the blocks of the frame.
Abstract:
A display driving method and an associated driving circuit are provided, where the display driving method includes: checking relationships between two voltage levels respectively represented by two continuously received digital codes received by a specific digital code input terminal and a first predetermined threshold, and preferably further checking a relationship between at least one voltage level represented by at least one digital code of the two continuously received digital codes and a first predetermined zone, in order to determine whether to pre-charge a specific set of display cells within a plurality of sets of display cells, the specific set corresponding to the specific digital code input terminal; when it is determined to pre-charge the specific set of display cells, temporarily conducting a pre-charging voltage generator to the specific set of display cells to pre-charge the specific set of display cells.
Abstract:
A backlight module for a display device includes a clock generation module for generating a clock signal, a control module for generating a control signal and a selection control signal, a selection module coupled to the clock generation module and the control module for generating a selection result according to the clock signal and the control signal, and an output module coupled to the selection module for outputting the selection result according to the selection control signal, wherein the selection result controls the display device to be operated in a normal backlight mode, a transition mode or a flashing backlight mode.
Abstract:
A display apparatus includes a source driver and a display panel. The source driver provides a plurality of pixel voltages which respectively correspond to a maximum gray-level voltage or a minimum gray-level voltage. The display panel includes a plurality of data lines, a plurality of pixel switches, a plurality of pixel capacitors, and a plurality of gray-level switches. The data lines are coupled to the source driver to receive the pixel voltages. Each pixel switch is respectively coupled to the corresponding data line to transmit the corresponding pixel voltage. Each pixel capacitor is respectively coupled between the corresponding pixel switch and a common voltage to receive the corresponding pixel voltage. Each gray-level switch is respectively coupled to the corresponding pixel capacitor in parallel and respectively receives a gray-level control signal. The gray-level switches regulate voltage drops across the pixel capacitors according to the corresponding gray-level control signals.
Abstract:
The present invention discloses an integrated source driver for a liquid crystal display device. The integrated source driver includes a reference voltage generating circuit, for providing a plurality of adjustable voltage ranges within a supply voltage and a ground level, and a reference voltage selecting circuit, including a plurality of digital to analog converters, for selecting and generating a plurality of internal reference voltages from the plurality of adjustable voltage ranges, respectively. The plurality of adjustable voltage ranges decrease progressively.
Abstract:
A control method utilized in a clock data recovery device supporting a plurality of frequency bands, for controlling the clock data recovery device to select an operating frequency band from the plurality of frequency bands and to generate a recovery clock for generating retimed data, includes receiving a serial data stream with a data frequency; making each frequency band of the plurality of frequency bands correspond to a plurality of frequency band groups, wherein each frequency band group includes at least one frequency band and corresponds to different frequency ranges; selecting a frequency band group from the plurality of frequency band groups as a coarse-tuned frequency band group according to the data frequency and a locking voltage range; and selecting a frequency band from the plurality of frequency bands according to the data frequency, the locking voltage range and the coarse-tuned frequency band group for generating the recovery clock.