公开(公告)号：US12141465B2

公开(公告)日：2024-11-12

申请号：US17127376

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu

IPC: G06F3/06 ,  G06F12/02

Abstract: Systems, apparatuses, and methods related to object management in tiered memory systems are discussed. An example method can include determining a type of characteristic set for each of a plurality of memory objects to be written to a memory system. The memory system can include a first memory device and a second memory device. The method can further include configuring each of the plurality of memory objects to be written to the memory system in the first memory device or the second memory device based on the determination of the type of characteristic set associated with each of the plurality of memory objects. The method can further include writing each of the plurality of memory objects to the first memory device or the second memory device based on the configuration of each of the plurality of memory objects.

公开(公告)号：US12141059B2

公开(公告)日：2024-11-12

申请号：US18058132

申请日：2022-11-22

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio

IPC: G06F12/00 ,  G06F12/02

Abstract: Methods, systems, and devices for data separation for garbage collection are described. A control component coupled to the memory array may identify a source block for a garbage collection procedure. In some cases, a first set of pages of the source block may be identified as a first type associated with a first access frequency and a second set of pages of the source block ay be identified as a second type associated with a second access frequency. Once the pages are identified as either the first type or the second type, the first set of pages may be transferred to a first destination block, and the second set of pages may be transferred to a second destination block as part of the garbage collection procedure.

公开(公告)号：US20240371449A1

公开(公告)日：2024-11-07

申请号：US18635946

申请日：2024-04-15

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Yang Lu

IPC: G11C16/34

Abstract: Apparatuses and techniques for implementing usage-based disturbance mitigation counter control are described. In some examples, a mitigation counter controller manages mitigation of usage-based disturbances by mitigating one or more wordlines in a memory device that have been disturbed. The mitigation counter controller may access a usage-based disturbance counter by activating a single sub wordline driver in the wordline, where the usage-based disturbance counter is associated with usage-based disturbances of the wordline. Activation of a single sub wordline driver to access the usage-based disturbance counter may reduce power consumption and may simplify the design of the memory device.

公开(公告)号：US20240371410A1

公开(公告)日：2024-11-07

申请号：US18642796

申请日：2024-04-22

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Raghukiran Sreeramaneni ,  Nevil N. Gajera

IPC: G11C5/02 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: An apparatus including a high bandwidth memory circuit and associated systems and methods are disclosed herein. The apparatus may include multiple HBM cubes connected to a processor, such as a GPU. The HBM cubes may be connected in series or in parallel. One or more of the HBM cubes can include a secondary communication circuit configured to facilitate the expanded connection between the multiple cubes.

公开(公告)号：US20240370365A1

公开(公告)日：2024-11-07

申请号：US18643514

申请日：2024-04-23

Applicant: Micron Technology, Inc.

Inventor： David Aaron PALMER

IPC: G06F12/02

Abstract: In some implementations, a memory apparatus may receive a command indicating a logical block address (LBA) that is associated with a logical-to-physical (L2P) table. The memory apparatus may perform a lookup operation associated with a compressed version of an address range of the L2P table to identify a physical address in non-volatile memory associated with the LBA, wherein the compressed version is stored in a volatile memory of the memory apparatus, wherein the compressed version is associated with an exception list that indicates physical addresses for respective LBAs, included in the address range, that are associated with non-sequential physical addresses, and wherein the compressed version is associated with a binary tree that indicates locations in the exception list associated with the respective LBAs. The memory apparatus may perform, based on the command, an action associated with the physical address.

公开(公告)号：US20240370206A1

公开(公告)日：2024-11-07

申请号：US18773373

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Akira Goda ,  Jeffrey S. McNeil ,  Jung Sheng Hoei ,  Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Patrick R. Khayat

IPC: G06F3/06

Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.

公开(公告)号：US20240370183A1

公开(公告)日：2024-11-07

申请号：US18777080

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Qi Dong

IPC: G06F3/06

Abstract: The present disclosure includes apparatuses, methods, and systems for storing non-volatile memory initialization failures. In an example, a method can include initializing a volatile memory die, initializing a first non-volatile memory die in response to initializing the volatile memory die, copying executable instructions from the first non-volatile memory die to the volatile memory die in response to initializing the first non-volatile memory die, initializing the second non-volatile memory die in response to initializing the first non-volatile memory die, and storing a failure record in the first non-volatile memory die in response to an error occurring during the initialization of the second non-volatile memory die.

公开(公告)号：US20240369416A1

公开(公告)日：2024-11-07

申请号：US18646587

申请日：2024-04-25

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G01K1/022 ,  G01K1/02 ,  G05B19/042 ,  G06F16/2455

Abstract: Methods, systems, and devices for temperature exception tracking in a temperature log for a memory system are described. The memory system may store the temperature log separate from data to which the temperature information corresponds. For example, a memory device may store data in a relatively higher-level cell and the corresponding temperature information in a relatively lower-level cell. To perform a write operation, the memory system may determine a current temperature at which the data is being written or was written to a partition of a memory device and may indicate in the temperature log if the current temperature is entering a temperature range that is outside a threshold temperature (e.g., a nominal temperature). To perform a read operation, the memory system may determine if the data to read was written to the memory device outside the threshold temperature to determine whether to perform temperature compensation for the read operation.

公开(公告)号：US12137551B2

公开(公告)日：2024-11-05

申请号：US17950336

申请日：2022-09-22

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling

IPC: H10B12/00 ,  H01L21/308 ,  H01L21/762

Abstract: Some embodiments include an integrated assembly having a semiconductor-containing structure with a body region vertically between an upper region and a lower region. The upper region includes a first source/drain region. The lower region is split into two legs which are both joined to the body region. One of the legs includes a second source/drain region and the other of the legs includes a body contact region. The first and second source/drain regions are of a first conductivity type, and the body contact region is of a second conductivity type which is opposite to the first conductivity type. An insulative material is adjacent to the body region. A conductive gate is adjacent to the insulative material. A transistor includes the semiconductor-containing structure, the conductive gate and the insulative material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12135987B2

公开(公告)日：2024-11-05

申请号：US17075096

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Chris Baronne ,  Dean E. Walker ,  John Amelio

IPC: G06F9/48 ,  G06F9/30 ,  G11C7/10 ,  G11C7/22

Abstract: Devices and techniques for sharing thread memory in a barrel processor via scheduling are described herein. An apparatus includes a barrel processor, which includes thread scheduling circuitry, where the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to: place a thread to be scheduled in one of two groups: a first group and a second group, wherein the first group is associated with a first processor storage device, and the second group is associated with a second processor storage device; and schedule a current thread to place into a pipeline for the barrel processor, the scheduling performed by alternating between threads in the first group and threads in the second group.