公开(公告)号：US20020063307A1

公开(公告)日：2002-05-30

申请号：US09991555

申请日：2001-11-21

Applicant: STMicroelectronics S.r.I.

Inventor： Davide Patti

IPC: H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  H01L029/76 ,  H01L031/062 ,  H01L029/94 ,  H01L031/119 ,  H01L021/20 ,  H01L029/00 ,  H01L023/62 ,  H01L031/113 ,  H01L027/082 ,  H01L027/102 ,  H01L029/70 ,  H01L031/11

CPC classification number: H01L28/20 ,  H01L27/0802 ,  H01L29/8605

Abstract: A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity. In this way, either a resistive element presenting a substantially linear performance in all ranges of applied voltage or a resistive element presenting a marked increase of the resistance value as the applied voltage increases can be made. This all with the additional possibility of selectively varying the resistance value demonstrated before the increase.

Abstract translation: 一种用于半导体电阻元件的结构，特别适用于具有n型高浓度衬底，n型第一外延层，布置在所述第一外延层上的p型区域的功率元件，从而形成 电阻元件本体，在所述第一外延层上生长以使p型区域成为掩埋区域的n型第二外延层和相对于第二外延级别具有较高浓度的n型附加层，定位 在嵌入式区域。 提供适于为电阻器制造低电阻率深触点的p型低电阻率区域。 掩埋区域可以通过在其主要延伸方向上基本均匀的发展来实现，或者在其长度的一部分上呈现边缘连续性的相邻子区域的结构。 以这种方式，可以在所施加的电压的所有范围内呈现基本上线性的电阻元件，或者施加的电压增加时呈现电阻值的显着增加的电阻元件。 这一切都具有选择性地改变在增加之前显示的电阻值的附加可能性。

公开(公告)号：US20020054504A1

公开(公告)日：2002-05-09

申请号：US09957628

申请日：2001-09-19

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C016/04

CPC classification number: G11C11/5621 ,  G11C16/0416 ,  G11C2211/5641

Abstract: The multilevel memory device has a memory section containing cells that can be programmed with a predetermined number of levels greater than two, i.e., a multilevel array, and a memory section containing cells that can be programmed with two levels, i.e., a bilevel array. The multilevel array is used for storing high-density data, for which speed of reading is not essential, for example for storing the operation code of the system including the memory device. On the other hand, the bilevel array is used for storing data for which high speed and reliability of reading is essential, such as the BIOS of personal computers, and the data to be stored in a cache memory. The circuitry parts dedicated to programming, writing of test instructions, and all the functions necessary for the operation of the memory device, can be common to both arrays.

Abstract translation: 多电平存储器件具有存储器部分，该存储器部分包含可以以大于2的预定数量的级别（即，多级阵列）编程的单元，以及包含可以用两个级别编程的单元的存储器部分，即双层阵列。 多级阵列用于存储高密度数据，读取速度不是必需的，例如用于存储包括存储器件的系统的操作代码。 另一方面，双层阵列用于存储读取的高速度和可靠性至关重要的数据，例如个人计算机的BIOS以及要存储在高速缓冲存储器中的数据。 专用于编程，写入测试指令的电路部分以及存储器件操作所需的所有功能对于这两个阵列都是共同的。

公开(公告)号：US20020047694A1

公开(公告)日：2002-04-25

申请号：US09955735

申请日：2001-09-18

Applicant: STMicroelectronics S.r.I.

Inventor： Alessandro Zafarana ,  Claudia Castelli

IPC: G05F001/40

CPC classification number: H02M3/1584 ,  H02M2001/0009

Abstract: A voltage/current controller device, particularly for interleaving switching regulators, comprises: a DC/DC converter having a plurality of modules, with each module including a drive transistor pair connected in series between first and second supply voltage references, a current sensor connected to one transistor in the pair, and a current read circuit connected to the sensor. Advantageously, the read circuit comprises a transconductance amplifier connected across the current sensor to sense a voltage signal related to a load current being applied to each module, the transconductance amplifier reading the voltage signal with the transistor in the conducting state.

Abstract translation: 电压/电流控制器装置，特别是用于交错开关稳压器的电压/电流控制器装置包括：具有多个模块的DC / DC转换器，每个模块包括串联连接在第一和第二电源电压基准之间的驱动晶体管对，连接到 该对中的一个晶体管和连接到传感器的电流读取电路。 有利地，读取电路包括跨过电流传感器连接的跨导放大器，以感测与施加到每个模块的负载电流相关的电压信号，跨导放大器在晶体管处于导通状态下读取电压信号。

公开(公告)号：US20020036487A1

公开(公告)日：2002-03-28

申请号：US09912232

申请日：2001-07-24

Applicant: STMicroelectronics S.r.I.

Inventor： Ugo Moriconi ,  Claudio Adragna

IPC: G05F001/44

CPC classification number: H03K17/063 ,  H02M3/155

Abstract: Disclosed is a bootstrap circuit in DC/DC static converters having the characteristic of comprising a fixed frequency signal, a recharge circuit of a capacitor and current generator means, said generator means controlled so as to emit current pulses, in synchrony with said fixed frequency signal, of a predetermined duration, every time that charge accumulated by said capacitor goes below a predetermined level.

Abstract translation: 公开了一种DC / DC静态转换器中的自举电路，具有包括固定频率信号，电容器的再充电电路和电流发生器装置的特性，所述发生器装置被控制以与所述固定频率信号同步地发射电流脉冲 每当所述电容器累积的电荷低于预定电平时，具有预定持续时间。

公开(公告)号：US20010017564A1

公开(公告)日：2001-08-30

申请号：US09751927

申请日：2000-12-29

Applicant: STMicroelectronics S.r.I.

Inventor： Michelangelo Mazzucco ,  Vanni Poletto ,  Melano Carlo Lorenzo Protti

IPC: G06G007/18

CPC classification number: G01L23/225 ,  G06J1/00

Abstract: A circuit extends the output voltage range of an integrator circuit wherein the input signal is used to produce an output signal, and the voltage of the output signal develops monotonically within a predetermined range of possible values. The integrator circuit is driven within an integration time period such that each time the signal at its output reaches a limit of the range of values, the integrator circuit starts a subsequent integration stage of the input signal in which the output signal develops again within the above-mentioned range. This takes place by resetting the integrator circuit or by a reversal of the characteristic slope of the output signal. This is combined with storing the number of occasions on which these interventions have occurred as determined by a counter. This enables the actual voltage value of the signal resulting from the integration to be calculated by a relatively straightforward mathematical operation from the reading of the counter, and from the signal currently present at the output of the integrator at the end of the integration period.

Abstract translation: 电路扩展积分器电路的输出电压范围，其中输入信号用于产生输出信号，并且输出信号的电压在可能值的预定范围内单调发展。 积分电路在积分时间段内被驱动，使得每当其输出端的信号达到值范围的极限时，积分器电路开始输入信号的后续积分级，其中输出信号在上述范围内再次产生 提到的范围。 这通过复位积分器电路或反转输出信号的特性斜率来进行。 这与存储由柜台确定的这些干预发生的场合的数量相结合。 这使得通过来自计数器的读数的相对简单的数学运算以及在积分周期结束时当前存在于积分器的输出端的信号来计算由积分产生的信号的实际电压值。

公开(公告)号：US20240429928A1

公开(公告)日：2024-12-26

申请号：US18824653

申请日：2024-09-04

Applicant: STMicroelectronics S.r.I.

Inventor： Agatino Massimo Maccarrone ,  Antonino Conte ,  Francesco Tomaiuolo ,  Michelangelo Pisasale ,  Marco Ruta

IPC: H03M1/06

Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror comprising a first plurality of MOS transistors and a second plurality of MOS transistors, wherein ones of the second plurality of MOS transistors are coupled between adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.

公开(公告)号：US20240061025A1

公开(公告)日：2024-02-22

申请号：US18493494

申请日：2023-10-24

Applicant: STMicroelectronics S.r.I

Inventor： Paolo Angelini

IPC: G01R19/25 ,  G01R15/14

CPC classification number: G01R19/25 ,  G01R15/146

Abstract: In accordance with an embodiment, a method of measuring a load current flowing through a current measurement resistor coupled between a source node and a load node includes: measuring a first voltage across a replica resistor when a first end of the replica resistor is coupled to the source node and a second end of the replica resistor is coupled to a reference current source; measuring a second voltage across the replica resistor when the second end of the replica resistor is coupled to the source node and the first end of the replica resistor is coupled to the reference current source; measure a third voltage across the current sensing resistor; and calculating a corrected current measurement of the load current based on the measured first voltage, the measured second voltage and the measured third voltage.

公开(公告)号：US20230361727A1

公开(公告)日：2023-11-09

申请号：US18308850

申请日：2023-04-28

Applicant: STMicroelectronics S.r.I.

Inventor： Gaetano Cosentino

IPC: H03G3/30 ,  H03F3/19

CPC classification number: H03F3/19 ,  H03G3/30 ,  H03F2200/451 ,  H03G2201/103

Abstract: A circuit includes an amplifier and a feedback network coupled between the input and the output of the amplifier. The feedback network includes a plurality of parallel coupled branches, each branch having a first selection switch coupled to the input, a second selection switch coupled to the output, and an impedance between the first and second selection switches. Each branch includes a plurality of signal feedback paths coupled in parallel, each having a tuning switch coupled between the first selection switch and the second selection switch of that branch. A control unit is coupled to the feedback network and configured to vary a gain of the amplifier by selectively placing the first and second selection switches of each branch in a conductive state or a non-conductive state and selectively activating respective tuning switches of any branch having first and second selection switches in the conductive state.

公开(公告)号：US20230130268A1

公开(公告)日：2023-04-27

申请号：US17933972

申请日：2022-09-21

Applicant: STMicroelectronics S.r.I.

Inventor： Marco Ruta ,  Antonino Conte ,  Michelangelo Pisasale ,  Agatino Massimo Maccarrone ,  Francesco Tomaiuolo

IPC: G05F1/575 ,  H03K5/24 ,  H03K5/05

Abstract: A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.

公开(公告)号：US11595039B2

公开(公告)日：2023-02-28

申请号：US17658016

申请日：2022-04-05

Applicant: STMicroelectronics S.r.I.

Inventor： Noemi Gallo ,  Edoardo Botti

IPC: H03K17/00 ,  H03K17/56 ,  H03K19/20 ,  H03K17/687

Abstract: A circuit includes a high-side switch and a low-side switch. A first inverter includes first and second discharge current paths activatable to sink first and second discharge currents, respectively, from the control terminal of the high-side switch. A second inverter includes first and second charge current paths activatable to source first and second charge currents to the control terminal of the low-side switch. A high-side sensing current path includes an intermediate high-side control node, and a low-side sensing current path includes an intermediate low-side control node. The second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.