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公开(公告)号：US20240116631A1
公开(公告)日：2024-04-11
申请号：US18045194
申请日：2022-10-10
Inventor： Christopher E. Kohl , Jeffrey A. Gensler , Parker T. Hyink
Abstract: Various countermeasure dispensing systems (or CMDSs) and method of use are described herein. CMDS may include a dispenser assembly operably engaged with a platform where at least one electrical connection provides electrical communication between the dispenser assembly and a sequencer. CMDS may also include a magazine assembly operably engaged with the dispenser assembly, wherein the magazine assembly comprises a magazine configured to hold at least two countermeasure expendables. CMDS may also include a breechplate assembly operably engaged with the magazine assembly and adapted to dispense the at least two countermeasure expendables. CMDS may also include at least one magazine identification switch (MIS) operably engaged with the magazine assembly and the breechplate assembly. CMDS may also include that the at least one MIS is configured to enable the sequencer and the breechplate assembly to selectively dispense at least one countermeasure expendable from the at least two countermeasure expendables.
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公开(公告)号：US11956162B2
公开(公告)日：2024-04-09
申请号：US18169418
申请日：2023-02-15
Inventor： Matthew J. Sherman , Mark D. Chauvette , Matthew Rasa , Nicholas C. Sherman
IPC: H04L47/72 , H04L7/00 , H04L41/5003 , H04L47/56 , H04W48/16 , H04W72/0446
CPC classification number: H04L47/72 , H04L7/0008 , H04L41/5003 , H04L47/56 , H04W48/16 , H04W72/0446
Abstract: An asynchronous medium access control layer scheduler increases efficiency for directional mesh networks by removing extra overhead in the time slots. The efficiency is increased by dividing time slots into sub-slots to allow for a receiving node to be offset by at least one sub-slot from the transmitting node. This enables the scheduler to more efficiently schedule operations for the nodes so that nodes can be performing other functions rather than waiting to receive a transmission or waiting after transmitting a transmission. The sub-slots may be sized to approximate the transmission propagation time or time of flight delay.
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公开(公告)号：US11953294B1
公开(公告)日：2024-04-09
申请号：US17462189
申请日：2021-08-31
Inventor： David A. Barfoot , Mark A. Frank , David L. Oles
CPC classification number: F41H11/02 , F41H13/0056 , G01C21/16
Abstract: A system and methods of an active protection system (or “APS”) for a platform. The APS has a threat cueing sensor provided at a first position on the platform where the threat cueing sensor detects a threat launched from a threat guidance system at a distance away from the platform. The APS also has a logic system operably connected to the threat cueing sensor where the logic system is adapted to determine an estimated location of the threat guidance system via a distance away from the platform. The APS also has a laser source operably connected to the logic system where the laser source emits a countermeasure beam directed at the estimated location of the threat guidance system to deter the threat away from the platform.
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公开(公告)号：US11899491B1
公开(公告)日：2024-02-13
申请号：US17953992
申请日：2022-09-27
Inventor： Matthew J. Sherman , Mritunjay Sinha , Lawrence Yang
CPC classification number: G06F1/12 , G06F15/7814 , H04J3/0635
Abstract: The system and method generates a pulse or a signal that is transmitted between a central processing unit or processor and an Ethernet integrated circuit card to program a trigger generator in the IC. The pulse is effectively a 1PPS signal that is provided to the IC, which may be in the form a field programmable gate array to enable timing synchronization. The trigger in the IC may also generates an interrupt to the processor so a driver in the CPU is instructed to set the next trigger. For the trigger to be accurately controlled, the control routine is implemented in the driver existing in kernel space rather than user space. A routine or protocol periodically polls the interrupt to determine when the trigger must be reset.
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公开(公告)号：US11867908B2
公开(公告)日：2024-01-09
申请号：US17554603
申请日：2021-12-17
Inventor： R. Daniel McGrath
CPC classification number: G02B27/0172 , G02B30/35 , H04N13/332 , H04N23/80 , H04N23/90 , G02B30/36 , G02B2027/014 , G02B2027/0134 , G02B2027/0138
Abstract: A digital imaging system is provided with direct view of an object, having: an optical element configured to allow visible light to pass therethrough to a user's eye and to redirect light of non-visible wavelengths away from the user's eye; a display disposed between the user's eye and the object; a digital camera mounted outside a field of view of the user's eye and configured to obtaining imaging data from the light of non-visible wavelength; a redirection optic disposed so as to redirect the light of non-visible wavelength to the digital camera; and an image processor configured to process the imaging data from the digital camera and output the data to the display such that an image generated from the imaging data from the digital camera overlays an image produced by the impingement of visible light on the user's eye following the visible light's passing through the optical element.
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Patent Agency Ranking
公开(公告)号：US11861181B1
公开(公告)日：2024-01-02
申请号：US17818850
申请日：2022-08-10
Inventor： David D. Moser , Richard J. Ferguson , Daniel L. Stanley
CPC classification number: G06F3/0619 , G06F3/0652 , G06F3/0653 , G06F3/0673 , G06F11/0772 , G06F11/141
Abstract: Techniques are provided for a radiation hardened memory system. A memory system implementing the techniques according to an embodiment includes a redundancy comparator configured to detect differences between data stored redundantly in a first memory, a second memory, and a third memory. The redundancy comparator is further configured to identify a memory error based on the detected differences. The memory system also includes an error collection buffer configured to store a memory address associated with the memory error, and a memory scrubber circuit configured to overwrite, at the memory address associated with the memory error, erroneous data with corrected data. The corrected data is based on a majority vote among the three memories. The memory system further includes a priority arbitrator configured to arbitrate between the memory scrubber overwriting and functional memory accesses associated with software execution performed by a processor configured to utilize the memory system.
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公开(公告)号：US11859956B2
公开(公告)日：2024-01-02
申请号：US17263955
申请日：2019-08-30
Inventor： Paul Zemany , Matthew Chrobak
Abstract: A guided projectile including a precision guidance munition assembly utilizes at least one maneuver envelope to optimally control movement of at least one canard to steer the guided projectile during flight. The maneuver envelopes optimize movements of the at least one canard that effectuate movement in either the range direction or the cross-range direction, or both. The maneuver envelope enables optimal timing such that maneuvering in one direction does not come at the expense of maneuver authority in the other direction.
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38.发明公开公开(公告)号：US20230421425A1
公开(公告)日：2023-12-28
申请号：US17847896
申请日：2022-06-23
Inventor： Christopher N. Peters , David D. Moser
CPC classification number: H04L27/2651 , G06F17/142
Abstract: Techniques are provided for a fast Fourier transform (FFT) sample reorder circuit for a dynamically reconfigurable oversampled channelizer. An FFT sample reorder circuit implementing the techniques according to an embodiment includes a plurality of dual port memory circuits. The circuit also includes a first crossbar circuit configured to route input data samples to write ports of the plurality of dual port memory circuits. The circuit further includes a second crossbar circuit configured to route reordered output data samples from read ports of the plurality of dual port memory circuits to a multi-stage FFT circuit. The circuit further includes a controller circuit configured to control the routing of the input data samples and the routing of the reordered output data samples based on a selection of a stage of the multi-stage FFT circuit.
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公开(公告)号：US20230421137A1
公开(公告)日：2023-12-28
申请号：US17847892
申请日：2022-06-23
Inventor： Christopher N. Peters , David D. Moser
CPC classification number: H03H17/0227 , G06F7/523 , G06F7/50
Abstract: Techniques are provided for a polyphase filtering in a dynamically reconfigurable two times (2×) oversampled channelizer. A polyphase filter implementing the techniques according to an embodiment includes a first plurality of dual port memory circuits and a multiplexer circuit configured to distribute input data for storage to the first plurality of dual port memory circuits. The polyphase filter also includes a second plurality of dual port memory circuits configured to store polyphase filter coefficients and a data alignment crossbar circuit configured to align the input data stored in the first plurality of dual port memory circuits with the polyphase filter coefficients stored in the second plurality of dual port memory circuits. The polyphase filter further includes a multiply circuit configured to perform multiplications of the aligned input data with the polyphase filter coefficients and an adder circuit to sum the results of the multiplications to generate a filtered output.
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公开(公告)号：US20230418898A1
公开(公告)日：2023-12-28
申请号：US17847887
申请日：2022-06-23
Inventor： Christopher N. Peters , David D. Moser
CPC classification number: G06F17/142 , H04B1/18 , H04L25/03828 , H03H17/0223
Abstract: Techniques are provided for a dynamically reconfigurable two times (2×) oversampled channelizer. A channelizer implementing the techniques according to an embodiment includes a polyphase filter, a two phase reorder circuit, a fast Fourier transform (FFT) circuit, and a two phase merge circuit. The polyphase filter is configured to filter time domain input data to control spectral shaping of frequency bins of the channelizer output. The two phase reorder circuit is configured to split a 2× oversampled data stream into two parallel, critically sampled data streams. The FFT circuit is configured to transform each stream into the frequency domain. The two phase merge circuit is configured to merge the two streams of frequency domain data into a single stream of 2× oversampled frequency domain data for distribution onto frames of frequency bins. Reconfigurable parameters for the channelizer include filter coefficients, number of filter folds, and number of frequency bins.
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