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公开(公告)号：US07176733B2
公开(公告)日：2007-02-13
申请号：US11009534
申请日：2004-12-10
申请人： Dieter Haerle
发明人： Dieter Haerle
IPC分类号： H03L7/06
CPC分类号： H03L7/0895 , H03L7/0812
摘要： A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.
摘要翻译： 用于锁相环/延迟锁定环的电荷泵通过使用运算放大器将静态相位误差最小化。 运算放大器还可以减轻低电源电压的影响。
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公开(公告)号：US07136961B2
公开(公告)日：2006-11-14
申请号：US10357270
申请日：2003-01-31
申请人： Alan Roth , Robert McKenzie , Oswald Becca
发明人： Alan Roth , Robert McKenzie , Oswald Becca
IPC分类号： G06F12/00
摘要： A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.
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公开(公告)号：US06959346B2
公开(公告)日：2005-10-25
申请号：US09741829
申请日：2000-12-22
申请人： Arthur John Low , Stephen J. Davis
发明人： Arthur John Low , Stephen J. Davis
CPC分类号： H04L67/42 , H04L49/90 , H04L49/9036 , H04L63/0428 , H04L63/0485 , H04L67/34 , H04L69/22 , H04L69/329
摘要： A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list processes to perform on the packet of data and am ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is not next process for a packet at which time it is provided to an output port.
摘要翻译： 公开了一种用于处理数据的数据处理器和方法。 处理器具有用于接收待处理数据的数据包的输入端口。 主控制器用于分析数据包，并提供一个报头，其中包括对数据包执行的列表进程和序列。 主控制器被编程有与处理器的整体处理功能相关的过程相关数据。 标题附加到数据包。 具有附加标题信息的分组被存储在缓冲器中。 缓冲器控制器用于基于分组内的报头来确定存储在缓冲器内的每个分组，以处理分组的下一个处理器。 然后，控制器将该分组提供给所确定的处理器进行处理。 返回处理后的数据包，表示处理完成。 例如，可以从进程列表中删除该进程。 缓冲器控制器重复地确定下一个处理，直到在其被提供给输出端口的分组没有下一个处理。
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公开(公告)号：US20040123024A1
公开(公告)日：2004-06-24
申请号：US10386378
申请日：2003-03-10
发明人： Lawrence King
IPC分类号： G06F012/00
CPC分类号： H04L45/00 , G11C15/00 , H04L45/7453
摘要： A plurality of entities are stored in a single addressable location in a Content Addressable Memory (CAM). A column in a CAM entry is selected for storing an entity based on the property of the entity to distribute the entities among the columns to maximize memory utilization. A match for a search key stored in one of the plurality of columns can be found in a single search operation.
摘要翻译： 多个实体存储在内容可寻址存储器（CAM）中的单个可寻址位置中。 选择CAM条目中的列以基于实体的属性存储实体以在列之间分布实体以最大化内存利用率。 可以在单个搜索操作中找到存储在多个列之一中的搜索关键字的匹配。
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35.发明申请Method and apparatus for wide word deletion in content addressable memories 有权内容可寻址存储器中用于宽字删除的方法和装置公开(公告)号：US20040093462A1
公开(公告)日：2004-05-13
申请号：US10357270
申请日：2003-01-31
发明人： Alan Roth , Robert McKenzie , Oswald Becca
IPC分类号： G06F012/00
摘要： A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.
摘要翻译： 公开了一种用于搜索和删除CAM阵列中的分段宽字条目的系统和方法。 执行正常的CAM搜索操作以找到宽字的第一字段。 一旦找到，执行搜索和删除操作，以沿着第一CAM阵列方向找到宽字的所有连续字段，其中最后一个字段被标记为删除的字段。 一旦最后一个字段被删除，宽字被认为已被删除，因为后续搜索宽字不会找到其最后一个字段。 然后沿着相反的CAM阵列方向执行清除操作，以删除所删除的宽字的所有字段。 CAM阵列的每一行中的匹配处理电路可以将搜索结果传递到其上方或下方的相邻行，以确保在搜索和删除操作中仅找到属于宽字的字段，并在清除操作中删除。
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公开(公告)号：US20040088476A1
公开(公告)日：2004-05-06
申请号：US10286743
申请日：2002-10-31
发明人： Mourad Abdat
IPC分类号： G06F012/00
CPC分类号： G06F7/02 , G06F7/24 , G06F2207/025 , G11C15/00 , Y10S707/99937
摘要： Method and apparatus using a Content Addressable Memory for sorting a plurality of data items is presented. The data items to be sorted are stored in the Content Addressable Memory. A plurality of bit-by-bit burst searches are performed on the contents of the Content Addressable Memory with all other bits in the search key masked. The number of burst searches is proportional to the total number of bits in the data items to be sorted. The search is deterministic dependent on the number of bits in each data item on which a sort is performed and on the number of data items to be sorted.
摘要翻译： 提出了使用内容可寻址存储器对多个数据项进行排序的方法和装置。 要排序的数据项存储在内容可寻址存储器中。 对内容可寻址存储器的内容执行多个逐位突发搜索，其中掩码的搜索关键字中的所有其他位。 突发搜索的数量与要排序的数据项中的总位数成比例。 搜索是确定性的，取决于执行排序的每个数据项中的位数以及要排序的数据项的数量。
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公开(公告)号：US20040042241A1
公开(公告)日：2004-03-04
申请号：US10234033
申请日：2002-08-30
发明人： Robert N. McKenzie , Dieter Haerle , Sean Lord
IPC分类号： G11C015/00
CPC分类号： G11C15/043 , G11C15/00 , G11C15/04
摘要： A Content Addressable Memory array includes a plurality of coupled sub-blocks arranged in rows and columns. Search data received by a first sub-block in a first column of the CAM is propagated to each sub-block in the row to the last sub-block in the last column of the CAM. The search result for the CAM is selected based on the propagated search results for each row of sub-blocks and output on a side of the array opposite from the side receiving the search data.
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38.发明申请Method and apparatus for processing arbitrary key bit length encryption operations with similar efficiencies 有权用于处理类似效率的任意密钥位长加密操作的方法和装置公开(公告)号：US20040039922A1
公开(公告)日：2004-02-26
申请号：US10228151
申请日：2002-08-26
发明人： Hafid Zaabab
IPC分类号： G06F012/14
CPC分类号： G06F7/728
摘要： A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.
摘要翻译： 具有多个级的计算装置或系统，例如在管道装置中，具有定时轨道或者导体位于该级的旁边。 具有排列成并行子阵列的大量，即数百个级，时钟导体与子阵列一起被蛇形。 在单个阶段，排列是在一个阶段中进行的最短的两次计算发生在返回路径中。 阵列可分为独立的部分，用于独立处理。
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公开(公告)号：US20030142668A1
公开(公告)日：2003-07-31
申请号：US10066550
申请日：2002-01-31
发明人： Richard M. Wyatt
IPC分类号： H04L012/56
CPC分类号： H04L45/74 , H04L45/745 , H04L45/7453 , H04Q3/68 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13167
摘要： A multistage switch includes a matrix of coupled switch devices. A logical link comprising a plurality of physical links couples a destination through the plurality of physical links to a plurality of ports in the multistage switch. Each switch device performs trunk aware forwarding to reduce the forwarding of received frames through the matrix of coupled switch devices to the destination in order to reduce unnecessary traffic in the multistage switch.
摘要翻译： 多级开关包括耦合开关器件的矩阵。 包括多个物理链路的逻辑链路通过多个物理链路将目的地耦合到多级交换机中的多个端口。 每个交换机设备执行中继线转发，以减少通过耦合的交换设备矩阵将接收的帧转发到目的地，以便减少多级交换机中的不必要的业务。
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公开(公告)号：US20030133347A1
公开(公告)日：2003-07-17
申请号：US10278195
申请日：2002-10-22
发明人： Richard C. Foss
IPC分类号： G11C007/02
CPC分类号： G11C7/1069 , G11C7/06 , G11C7/1048 , G11C7/1051 , G11C11/4091 , G11C11/4093 , G11C11/4096 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.
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