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    Synchronous rectifier having precise on/off switching times
    31.
    发明授权
    Synchronous rectifier having precise on/off switching times 有权
    同步整流器具有精确的开/关切换时间

    公开(公告)号：US08013586B2

    公开(公告)日：2011-09-06

    申请号：US11961401

    申请日：2007-12-20

    Applicant: Ondrej Tlaskal ,  Bohumil Janik ,  David Burda ,  Julien Picq ,  Miroslav Hukel

    Inventor： Ondrej Tlaskal ,  Bohumil Janik ,  David Burda ,  Julien Picq ,  Miroslav Hukel

    IPC: G05F1/00

    CPC classification number: H02M1/38 ,  H02M3/1588 ,  H02M2001/0009 ,  Y02B70/1466

    Abstract: A synchronous rectifier, including an energy storage element having a terminal; a power supply input, connected to the terminal of the storage element in a first time interval; a reference line connected to the terminal of the storage element in a second time interval; and a zero comparator, coupled to the terminal of the storage element to detect a current flowing in the energy storage element and disconnect the terminal of the storage element from the reference line upon detecting a zero current, the zero comparator having an offset and a propagation time; the zero comparator further having an offset control input and an output. An offset regulating loop is coupled between the output of the zero comparator and the offset control input and regulates the offset of the zero comparator to compensate the propagation time.

    Abstract translation: 一种同步整流器，包括具有端子的能量存储元件; 电源输入，在第一时间间隔连接到所述存储元件的终端; 在第二时间间隔连接到所述存储元件的终端的参考线; 以及零比较器，耦合到存储元件的端子以检测流过能量存储元件的电流，并且在检测到零电流时将存储元件的端子与参考线断开，零比较器具有偏移和传播 时间; 零比较器还具有偏移控制输入和输出。 偏移调节回路耦合在零比较器的输出和偏移控制输入之间，并调节零比较器的偏移量以补偿传播时间。

    LOGIC LEVEL CONVERTER
    32.
    发明申请
    LOGIC LEVEL CONVERTER 有权
    逻辑电平转换器

    公开(公告)号：US20100156499A1

    公开(公告)日：2010-06-24

    申请号：US12621380

    申请日：2009-11-18

    Applicant: Tomas JERABEK ,  Karel Napravnik

    Inventor： Tomas JERABEK ,  Karel Napravnik

    IPC: H03L5/00

    CPC classification number: H03K19/018521 ,  H03K3/356113

    Abstract: A logic level converter includes two first electronic switches coupled in a bi-stable flip-flop arrangement having at least one output line, and a forcing circuitry including two second electronic switches to force switching of the first electronic switches in the flip-flop arrangement. The forcing circuitry has an input terminal to receive a logic input signal having a given level to produce switching of the flip-flop arrangement and generate at the output line(s) of the flip-flop arrangement, a logic output signal(s) whose voltage level is converted with respect to the level of the logic input signal. The converter includes, interposed between each of the two first electronic switches in the flip-flop arrangement and a respective one of the second electronic switches in the forcing circuitry, at least one respective cascode electronic switch to limit the voltage across the two first electronic switches in the flip-flop arrangement.

    Abstract translation: 逻辑电平转换器包括耦合在具有至少一个输出线的双稳态触发器装置中的两个第一电子开关，以及包括两个第二电子开关以强制在触发器装置中切换第一电子开关的强制电路。 强制电路具有用于接收具有给定电平的逻辑输入信号的输入端以产生触发器装置的切换并在触发器装置的输出线处产生逻辑输出信号，其逻辑输出信号 电压电平相对于逻辑输入信号的电平被转换。 转换器包括插入在触发器装置中的两个第一电子开关中的每一个和强制电路中的相应一个第二电子开关中的至少一个相应的共源共栅电子开关以限制两个第一电子开关 在触发器安排。

    LOW-DROPOUT LINEAR REGULATOR AND CORRESPONDING METHOD
    33.
    发明申请
    LOW-DROPOUT LINEAR REGULATOR AND CORRESPONDING METHOD 有权
    低压差线性稳压器和相应的方法

    公开(公告)号：US20100148736A1

    公开(公告)日：2010-06-17

    申请号：US12621273

    申请日：2009-11-18

    Applicant: Karel Napravnik

    Inventor： Karel Napravnik

    IPC: G05F1/00

    CPC classification number: G05F1/575

    Abstract: A low-dropout linear regulator includes an error amplifier comprising a cascaded arrangement of a differential amplifier and a gain stage having interposed therebetween a frequency compensation network for a loading current to flow therethrough. The regulator includes a current limiter inserted the flow-path of the loading current for the compensation network to increase the slew rate of the output of the differential amplifier by dispensing with the capacitive load in the frequency compensation network during load transients in the regulator.

    Abstract translation: 低压差线性调节器包括误差放大器，该误差放大器包括差分放大器和增益级的级联布置，其间插入有用于流过其中的负载电流的频率补偿网络。 调节器包括限流器，其插入用于补偿网络的负载电流的流动路径，以通过在调节器中的负载瞬变期间分配频率补偿网络中的容性负载来增加差分放大器的输出的压摆率。

    FLEXIBLE LAYOUT FOR INTEGRATED MASK-PROGRAMMABLE LOGIC DEVICES AND MANUFACTURING PROCESS THEREOF
    34.
    发明申请
    FLEXIBLE LAYOUT FOR INTEGRATED MASK-PROGRAMMABLE LOGIC DEVICES AND MANUFACTURING PROCESS THEREOF 有权
    集成式可编程逻辑器件的灵活布局及其制造工艺

    公开(公告)号：US20090166683A1

    公开(公告)日：2009-07-02

    申请号：US12343621

    申请日：2008-12-24

    Applicant: Patrik VACULA ,  Milos VACULA ,  Milan LZICAR

    Inventor： Patrik VACULA ,  Milos VACULA ,  Milan LZICAR

    IPC: H01L29/66 ,  H01L21/00

    CPC classification number: H03K19/17736 ,  H03K19/1735 ,  H03K19/17796

    Abstract: Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between the first intermediate and the top metal levels and connecting each metal level to adjacent metal levels. The plurality of metal levels forms a first, a second and at least a third terminal, the top and bottom metal levels having at least two metal regions, and the first intermediate metal level having at least three metal regions. The first terminal is connected to third terminal or the second terminal is connected to the third terminal by modifying a single metal or via level.

    Abstract translation: 集成掩模可编程装置，具有多个金属层，包括形成在顶部和底部金属层之间的顶部金属层，底部金属层和第一中间金属层，以及布置在底部和底部金属层之间的多个通孔层 中间金属水平和第一中间和顶部金属水平之间并且将每个金属水平连接到相邻的金属水平。 多个金属层形成第一，第二和至少第三端子，顶部和底部金属层具有至少两个金属区域，并且第一中间金属层具有至少三个金属区域。 第一端子连接到第三端子，或者通过修改单个金属或通孔电平将第二端子连接到第三端子。

    Method and apparatus for quick prototyping of embedded peripherals
    40.
    发明授权
    Method and apparatus for quick prototyping of embedded peripherals 有权

    公开(公告)号：US11354100B2

    公开(公告)日：2022-06-07

    申请号：US16941407

    申请日：2020-07-28

    Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

    Inventor： Mahesh Chowdhary ,  Miroslav Batek ,  Marian Louda

    IPC: G06F8/34 ,  G06F8/36 ,  H04L67/00 ,  H04L67/12

    Abstract: The disclosure describes methods and apparatus for quickly prototyping of a solution developed using one or more sensing devices (e.g., sensors), functional blocks, algorithm libraries, and customized logic. The methods produce firmware executable by a processor (e.g., a microcontroller) on an embedded device such as a development board, expansion board, or the like. By performing these methods on the apparatus described, a user is able to create a function prototype without having deep knowledge of the particular sensing device or any particular programming language. Prototypes developed as described herein enable the user to rapidly test ideas and develop sensing device proofs-of-concept. The solutions produced by the methods and apparatus improve the functioning of the sensor being prototyped and the operation of the embedded device where the sensor is integrated.

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