公开(公告)号：US07408827B1

公开(公告)日：2008-08-05

申请号：US11303067

申请日：2005-12-14

申请人： Tao Peng ,  Rajesh Venugopal

发明人： Tao Peng ,  Rajesh Venugopal

IPC分类号： G11C7/02

CPC分类号： G11C7/08 ,  G11C7/062

摘要： Disclosed herein is a current sense amplifier (ISA) circuit with increased speed, less insensitivities to process variation, better stability and improved output signal swing. According to one embodiment, the ISA circuit described herein may include a pair of output nodes and a first pair of load transistors, each coupled between a different one of the output nodes and ground for pulling the output nodes down to a first voltage value at the beginning of a sense cycle. In addition, a pulse generation circuit is included for activating the first pair of load transistors at the beginning of the sense cycle and deactivating the first pair of load transistors once the first voltage is reached. When activated, the first pair of load transistors provide a relatively low resistance current path between the output nodes and ground. This decreases the output node discharge time and increases the overall speed of the sense amp without compromising circuit stability and output swing.

摘要翻译： 本文公开了具有增加的速度的电流读出放大器（ISA）电路，对处理变化的不敏感性，更好的稳定性和改善的输出信号摆幅。 根据一个实施例，本文描述的ISA电路可以包括一对输出节点和第一对负载晶体管，每对负载晶体管耦合在不同的输出节点和地之间，用于将输出节点向下拉到第一电压值 感觉周期的开始 此外，包括在感测周期开始时激活第一对负载晶体管的脉冲发生电路，一旦达到第一电压就停用第一对负载晶体管。 当被激活时，第一对负载晶体管在输出节点和地之间提供相对较低的电阻电流路径。 这会降低输出节点放电时间，并增加感测放大器的总体速度，而不会影响电路稳定性和输出摆幅。

公开(公告)号：US07404154B1

公开(公告)日：2008-07-22

申请号：US11189026

申请日：2005-07-25

申请人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl Anthony Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary Scott Delp ,  Scott Allen Peterson

发明人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl Anthony Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary Scott Delp ,  Scott Allen Peterson

IPC分类号： G06F17/50

CPC分类号： H03K19/1735 ,  G06F2217/64 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807

摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

摘要翻译： 提供了一种基本单元电路架构，其具有可配置用于形成结构化ASIC内的逻辑器件和/或单/双端口存储器件的固定晶体管的多个单元。 通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。 电路架构可以实现单个电池内和/或跨多个电池的晶体管的互连。 互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。 此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。 通过具有形成逻辑电路元件，存储器件或两者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，并且更完全适用于现代SoC。

公开(公告)号：US07385053B2

公开(公告)日：2008-06-10

申请号：US11621209

申请日：2007-01-09

申请人： Ananda G. Lugade ,  Kurt D. Hoffacker ,  Adam J. Jenkins ,  Karri L. Michael-Ballard ,  Leonid Patsenker ,  Ewald Terpetschnig ,  Veronica D. Thomason ,  Ralph McDade

发明人： Ananda G. Lugade ,  Kurt D. Hoffacker ,  Adam J. Jenkins ,  Karri L. Michael-Ballard ,  Leonid Patsenker ,  Ewald Terpetschnig ,  Veronica D. Thomason ,  Ralph McDade

IPC分类号： C07D345/00 ,  C07D201/00 ,  C07D255/00 ,  C07H21/00 ,  C12Q1/68

CPC分类号： B82Y30/00 ,  C07B2200/11 ,  C07C243/28 ,  C07C303/22 ,  C07C303/32 ,  C07C315/04 ,  C07C319/18 ,  C07C319/22 ,  C07C381/02 ,  C07C2601/04 ,  C07D239/48 ,  C07K1/042 ,  C07K17/00 ,  G01N33/54353 ,  Y10S977/902 ,  C07C309/47 ,  C07C309/88 ,  C07C309/46 ,  C07C317/18 ,  C07C323/65 ,  C07C323/42 ,  C07C309/42

摘要： The present invention relates to improved covalent coupling of two or more entities such as biomolecules, polymer compositions, organic/inorganic molecules/materials, and the like, including their combinations, through one or more novel reactive groups attached to linker groups of 2-1000 atoms length. The present invention also contemplates the use of bifunctional bridge molecules to link two or more entities, wherein the functional groups of the bridge molecules are the novel reactive groups of the present invention.

摘要翻译： 本发明涉及两个或多个实体如生物分子，聚合物组合物，有机/无机分子/材料等的改进的共价偶联，包括其组合，通过连接到2-1000的连接基团上的一个或多个新的反应性基团 原子长度。 本发明还考虑使用双官能桥分子连接两个或多个实体，其中桥分子的官能团是本发明的新的反应性基团。

公开(公告)号：US07379503B2

公开(公告)日：2008-05-27

申请号：US10654266

申请日：2003-09-03

申请人： Nils Krumme ,  Harry Schilling ,  Georg Lohr

发明人： Nils Krumme ,  Harry Schilling ,  Georg Lohr

IPC分类号： H04L25/00 ,  H04B5/00

CPC分类号： H04L25/0202 ,  H04B17/309

摘要： A device for receiving digital signals comprising at least one receiving antenna, a measuring means for determining parameters of relevance to signal quality, a digitizer, and a signal-processing unit. The signal-processing unit is controlled to optimize the reception of the digital signals on the basis of the parameters determined by the measuring means. A signal-processing unit processes signals from the receiving antenna and a digitizer converts the processed signals so that the converted processed signals can be measured to determine their relevance signal quality; a transmitter conductor array coupled to the receiving unit can be controlled therefrom. Controlling the signal quality occurs using a dielectric or ferromagnetic materials, impedance elements, or actuators between the receiving antenna and the transmitter conductor array.

摘要翻译： 一种用于接收数字信号的装置，包括至少一个接收天线，用于确定与信号质量相关的参数的测量装置，数字转换器和信号处理单元。 控制信号处理单元以根据由测量装置确定的参数来优化数字信号的接收。 信号处理单元处理来自接收天线的信号，并且数字转换器转换处理的信号，使得可以测量经转换的处理信号以确定其相关信号质量; 可以控制耦合到接收单元的发射器导体阵列。 使用接收天线和发射器导体阵列之间的电介质或铁磁材料，阻抗元件或致动器来控制信号质量。

公开(公告)号：US07379314B1

公开(公告)日：2008-05-27

申请号：US11779347

申请日：2007-07-18

申请人： Dechang Sun

发明人： Dechang Sun

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： An improved Content Addressable Memory (CAM) architecture and method for operating the same is provided herein. The improved CAM architecture may generally include an array of memory cells arranged into rows and columns, where each row includes a number of memory cells configured for storing one word. In particular, the number of memory cells may be coupled to a plurality of local match lines which, when combined through a hierarchy of two or more logic gates, form a match line signal for the entire word. Dynamic logic is used within a compare portion of each memory cell to reduce the occurrence of functional failures. In addition, the improved method for operating the CAM reduces power consumption and peak current, and improves timing, by eliminating the need to restore the match line voltage to a preset voltage level before each new compare operation.

摘要翻译： 本文提供了改进的内容可寻址存储器（CAM）架构及其操作方法。 改进的CAM架构通常可以包括布置成行和列的存储器单元的阵列，其中每行包括被配置用于存储一个字的多个存储单元。 特别地，存储器单元的数量可以耦合到多个局部匹配线，当通过两个或多个逻辑门的层级组合时，它们形成整个字的匹配线信号。 在每个存储器单元的比较部分内使用动态逻辑来减少功能故障的发生。 此外，通过在每次新的比较操作之前，不需要将匹配线电压恢复到预设的电压电平，所以用于操作CAM的改进方法可降低功耗和峰值电流，并提高定时。

公开(公告)号：US07365403B1

公开(公告)日：2008-04-29

申请号：US10074884

申请日：2002-02-13

申请人： Krishnaswamy Ramkumar

发明人： Krishnaswamy Ramkumar

IPC分类号： H01L27/108

CPC分类号： H01L21/28282 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/3143 ,  H01L29/513 ,  H01L29/518

摘要： A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dielectric thickness of less than approximately 20 angstroms.

摘要翻译： 提供半导体形貌，其包括厚度等于或小于约10埃的二氧化硅层和布置在二氧化硅层上的氮化硅层。 此外，提供了一种方法，其包括在存在臭氧化物质的情况下在半导体形貌上生长氧化膜并在氧化物膜上沉积氮化硅膜。 在一些实施例中，该方法可以包括在第一温度下在第一室中生长氧化膜并将半导体形貌从第一室转移到第二室，同时将半导体形貌暴露于与第一温度基本相似的温度。 在任一实施例中，该方法可以用于形成包括具有小于约20埃的电等效氧化物栅极介电厚度的氧化物 - 氮化物栅极电介质的半导体器件。

公开(公告)号：US07352199B2

公开(公告)日：2008-04-01

申请号：US09788864

申请日：2001-02-20

申请人： Khushrav S. Chhor ,  Tae-Hee Lee

发明人： Khushrav S. Chhor ,  Tae-Hee Lee

IPC分类号： G01R31/26

CPC分类号： G11C29/48 ,  G11C5/04 ,  G11C29/1201 ,  G11C2029/1206 ,  H01L2224/48227

摘要： By decreasing the amount of card substrate required in a memory card to support the actual memory unit, the test interface of the card, which is usually removed before final assembly of the card, can be brought within the allowable length of the finished card and can, therefore, remain on the card permanently. Consequently, in the event of a field failure, the test interface remains available for testing the card and diagnosing the location and cause of the failure.

摘要翻译： 通过减少存储卡中支持实际存储单元所需的卡片基板的数量，通常在卡的最终组装之前通常被去除的卡的测试​​接口可以被带到成品卡的允许长度内，并且可以 因此，永久保留在卡上。 因此，在现场故障的情况下，测试接口仍然可用于测试卡并诊断故障的位置和原因。

公开(公告)号：US07346849B1

公开(公告)日：2008-03-18

申请号：US09826998

申请日：2001-04-03

申请人： Thomas P. Mulligan ,  Steve H. Kolokowsky ,  Timothy J. Harvey

发明人： Thomas P. Mulligan ,  Steve H. Kolokowsky ,  Timothy J. Harvey

IPC分类号： G06F3/00

CPC分类号： G06F8/41 ,  Y10S715/967

摘要： An apparatus, computer program, and method are disclosed for generating computer executable code. The code is compiled from a data set, and the data set is compiled by selecting a link within a comments portion of a text editor portion of a program. The data set can then be inserted into an applications program to form the computer executable code. The comments portion involves a line of text that is preceded by a comments designator and succeeded by at least one link word that is adapted for modification by an on-screen pointer. Any changes to the link word via a graphical user interface will correspondingly change fields within a data set, which preferably is also displayed within the same window as the comments portion. The fields of bits within the data set can be used to program a hardware device or system. One example of such a device is a programmable device, or general purpose interface circuit that is juxtaposed between, for example, a computer and a peripheral device.

摘要翻译： 公开了一种用于生成计算机可执行代码的装置，计算机程序和方法。 代码从数据集编译，并且通过选择程序的文本编辑器部分的注释部分中的链接来编译数据集。 然后将数据集插入到应用程序中以形成计算机可执行代码。 注释部分涉及一行文本，前面是一个注释指示符，并由至少一个适用于屏幕上指针修改的链接字成功。 通过图形用户界面对链接字的任何改变将相应地改变数据集内的字段，其优选地也在与注释部分相同的窗口内显示。 数据集中的位的字段可用于对硬件设备或系统进行编程。 这种装置的一个例子是可编程装置或与例如计算机和外围设备并置的通用接口电路。

公开(公告)号：US07329934B1

公开(公告)日：2008-02-12

申请号：US10850247

申请日：2004-05-20

申请人： William W. C. Koutny, Jr.

发明人： William W. C. Koutny, Jr.

IPC分类号： H01L21/82

CPC分类号： H01L27/222 ,  H01L21/3212 ,  H01L21/7684

摘要： A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material laterally adjacent to the metal layer during polishing. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. As such, the method may include reducing the mean surface roughness of a metal layer. For example, the method may include reducing the mean surface roughness of a metal layer by at least a factor of ten.

摘要翻译： 提供了一种降低金属层的表面粗糙度的方法。 在一些实施例中，该方法可以包括将金属层抛光到基本上高于金属层正下方布置的任何层的水平。 在一些情况下，包括金属层的半导体形貌可以在抛光期间基本上不存在与金属层横向相邻的任何材料。 在任一情况下，可以获得具有平均表面粗糙度小于在金属层沉积期间获得的平均表面粗糙度的金属层的半导体形貌。 因此，该方法可以包括降低金属层的平均表面粗糙度。 例如，该方法可以包括将金属层的平均表面粗糙度降低至少十倍。

公开(公告)号：US07327199B1

公开(公告)日：2008-02-05

申请号：US11233963

申请日：2005-09-23

申请人： David Kwong ,  Trung Tran

发明人： David Kwong ,  Trung Tran

IPC分类号： G01R35/00

CPC分类号： G01R31/31727 ,  G01R31/31701 ,  H03L7/0891 ,  H03L7/095

摘要： According to one embodiment, a phase-locked loop (PLL) device includes test circuitry for entering/exiting a test mode upon receiving a particular pulse train at a reference clock input of the PLL. In addition, exemplary methods are provided herein for entering a test mode and detecting loop filter leakage within the PLL. The methods described herein are performed without the use of a dedicated test pin.

摘要翻译： 根据一个实施例，锁相环（PLL）装置包括用于在PLL的参考时钟输入端接收到特定脉冲串时进入/退出测试模式的测试电路。 此外，本文提供了用于输入测试模式和检测PLL内的环路滤波器泄漏的示例性方法。 在不使用专用测试针的情况下执行本文描述的方法。