中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4992 records (took 0.052 seconds)

    SYSTEM AND METHOD FOR ADJUSTING FILTERING FOR TEXTURE STREAMING
    31.
    发明申请
    SYSTEM AND METHOD FOR ADJUSTING FILTERING FOR TEXTURE STREAMING 有权

    公开(公告)号：US20250005840A1

    公开(公告)日：2025-01-02

    申请号：US18345427

    申请日：2023-06-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Guennadi Riguer ,  Michal Adam Wozniak

    IPC: G06T15/04 ,  G06T3/40

    Abstract: A technique for texture filtering. A transition is made from a first mipmap corresponding to a first texture resolution to a second mipmap corresponding to a second texture resolution. The first texture resolution is lower than the second texture resolution. As compared to standard trilinear filtering, initiation of the transition is delayed by an offset (or bias), which serves to delay the initial use of the second mipmap until it has been loaded. Following initiation of the transition, first and second weightings are selected with a nonlinear filter, and the system interpolates between the first mipmap and the second mipmap by applying the weightings. During an initial portion of the transition, the nonlinear filter has a slope that is higher than that of the standard trilinear filter.

    APPARATUS AND METHODS FOR TRANSLATING TRANSACTIONS BETWEEN ONE OR MORE REQUESTING UNITS AND A TARGET UNIT
    32.
    发明申请
    APPARATUS AND METHODS FOR TRANSLATING TRANSACTIONS BETWEEN ONE OR MORE REQUESTING UNITS AND A TARGET UNIT 有权

    公开(公告)号：US20250004974A1

    公开(公告)日：2025-01-02

    申请号：US18345992

    申请日：2023-06-30

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： BUHENG XU ,  XIAO HAN ,  PHILIP NG ,  SHIWU YANG

    IPC: G06F13/42

    Abstract: An apparatus translates transaction requests using a bus protocol translation lookup table (LUT) that comprises bus protocol translation data. A bus protocol translation controller generates the outgoing translated transaction request by translating the incoming transaction request using the bus protocol translation data from the bus protocol translation LUT. The controller translates a received response from the target unit to a response in a first bus protocol for a corresponding requesting unit. Associated methods are also presented. In some examples, the bus protocol translation data corresponds to each of a plurality of requesting units for translating between an incoming transaction request sent via a first bus protocol to an outgoing translated transaction request sent via a second bus protocol for the at least one target unit.

    PROCESSOR WITH VIRTUALIZABLE SIGNAL MONITORS
    35.
    发明申请
    PROCESSOR WITH VIRTUALIZABLE SIGNAL MONITORS 有权

    公开(公告)号：US20250004806A1

    公开(公告)日：2025-01-02

    申请号：US18216310

    申请日：2023-06-29

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Mark Unruh Wyse ,  Anthony Thomas Gutierrez ,  Stephen Alexander Zekany ,  Paul Blinzer

    IPC: G06F9/455

    Abstract: A processing unit (e.g., a CPU) executes multiple processes, such as multiple virtual machines, wherein each process employs virtual signals and virtual signal monitors to support signaling between the process and one or more accelerators. A hardware signal manager (HSM) assigns each virtual signal to a physical signal of the system and assigns each virtual signal monitor to a physical signal monitor. Based on a process' interactions (e.g., signal operations) with a virtual signal monitor, the HSM executes corresponding interactions at the assigned physical signal monitor. The HSM thus virtualizes the physical signal monitors for the executing processes.

    LIMITED BIT TOGGLING FOR DATA BUS INVERSION
    36.
    发明申请
    LIMITED BIT TOGGLING FOR DATA BUS INVERSION 有权

    公开(公告)号：US20250004530A1

    公开(公告)日：2025-01-02

    申请号：US18345940

    申请日：2023-06-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gregg Donley

    IPC: G06F9/30

    Abstract: The disclosed device includes multiple data elements each configured to send a bit of a bit sequence by toggling at most half of a number of bits from a previously sent bit sequence. The bit sequence can first be biased and then XORed with the previously sent bit sequence. Various other methods, systems, and computer-readable media are also disclosed.

    Interrupt cache configuration
    38.
    发明授权
    Interrupt cache configuration 有权

    公开(公告)号：US12182611B2

    公开(公告)日：2024-12-31

    申请号：US18145457

    申请日：2022-12-22

    Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

    Inventor： Philip Ng ,  Anil Kumar

    IPC: G06F9/48 ,  G06F9/30 ,  G06F11/07

    Abstract: An apparatus includes an interrupt cache having cache storage configured to store a plurality of interrupts received from an interrupt source, the plurality of interrupts corresponding to a plurality of interrupt events configured for execution by the plurality of interrupt service routines and a cache manager component configured to generate an interrupt message for transmission to the processing unit, the interrupt message generated to include at least one interrupt of the plurality of interrupts from the cache storage.

    Channel routing for simultaneous switching outputs
    39.
    发明授权
    Channel routing for simultaneous switching outputs 有权

    公开(公告)号：US12176065B2

    公开(公告)日：2024-12-24

    申请号：US17849197

    申请日：2022-06-24

    Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

    Inventor： Xuan Chen ,  Chih-Hua Hsu ,  Pradeep Jayaraman ,  Abdussalam Aburwein

    IPC: G11C7/22 ,  G11C5/02 ,  G11C7/10 ,  G11C8/18

    Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.

Patent Agency Ranking