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公开(公告)号：US20250028933A1
公开(公告)日：2025-01-23
申请号：US18356091
申请日：2023-07-20
Applicant: Arm Limited
Inventor： Gerti Tuzi , Dibakar Gope
Abstract: Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to estimate an execution latency of a candidate neural network in a neural network architecture search (NAS) process.
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公开(公告)号：US12205663B2
公开(公告)日：2025-01-21
申请号：US16506662
申请日：2019-07-09
Applicant: Arm Limited
Inventor： Steve Ngueya Wandji , El Mehdi Boujamaa , Cyrille Nicolas Dray
Abstract: In a particular implementation, a circuit comprises: a first branch comprising a first transistor, where the first branch is configured to generate a first voltage; a second branch comprising a second transistor, where the second branch is configured to generate a second voltage; and a comparator configured to generate an output signal based on a comparison of the first and second voltages. Also, the output signal may be configured to regulate an output voltage of one or more negative charge pump circuits coupled to the circuit.
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公开(公告)号：US12204562B2
公开(公告)日：2025-01-21
申请号：US18152946
申请日：2023-01-11
Applicant: Arm Limited
Inventor： Thibaut Elie Lanois , Houdhaifa Bouzguarrou , Guillaume Bolbenes
IPC: G06F16/28 , G06F16/22 , G06F16/2457
Abstract: An apparatus has a data storage structure to store data items tagged by respective tag values and stores, in association with each data item, a respective tag group identifier to identify other data items having a same tag value within a collection of data items. The apparatus also has tag match circuitry to identify one or more hitting data items. Prioritisation circuitry is provided to select candidate data items which, relative to any other data items in the particular collection of data items having the same tag group identifier as the selected candidate data item is favoured according to an ordering of the data items. The prioritisation circuitry selects the one or more candidate data items before the identification of the hitting data items is available from the tag match circuitry. Data item selection circuitry selects a candidate data item for which the tag match circuitry detected a match.
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公开(公告)号：US20250021487A1
公开(公告)日：2025-01-16
申请号：US18711242
申请日：2022-04-28
Applicant: Arm Limited
Inventor： Richard Roy Grisenthwaite
IPC: G06F12/1009
Abstract: Memory management circuitry (28) supports two-stage address translation based on a stage-1 and stage-2 translation table structures. Stage-2 access permission information specified by a stage-2 translation table entry has an encoding specifying whether a corresponding memory region has a partially-read-only permission indicating that write requests to the memory region corresponding to the target intermediate address, issued when processing circuitry (4) is in a predetermined execution state, are permitted for a restricted subset of write request types (including metadata-updating write requests for updating access tracking metadata in translation table entries) but prohibited for other write request types. The memory management circuitry (28) rejects a memory access request when the stage-2 access permission information of a corresponding stage-2 translation table entry specifies the partially-read-only permission and the memory access request is a write request, other than the restricted subset of write request types, issued in the predetermined execution state.
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公开(公告)号：US20250021480A1
公开(公告)日：2025-01-16
申请号：US18350217
申请日：2023-07-11
Applicant: Arm Limited
Inventor： Natalya BONDARENKO , Stefano GHIGGINI , Kamil GARIFULLIN , Fabian GRUBER , . ABHISHEK RAJA , Devin S. LAFFORD
IPC: G06F12/0811 , G06F12/0862 , G06F12/0871
Abstract: Apparatuses, methods, systems, and chip-containing products are disclosed, which relate to an arrangement comprising a level N cache level and a level M cache level, where M is greater than N. The level N cache level comprises a plurality of linefill slots and performs a slot allocation procedure in response to a lookup miss in dependence on a linefill slot occupancy criterion. The slot allocation procedure comprises allocation of an available slot of the plurality of slots to a pending linefill request generated in response to the lookup miss. The level N cache level effects a modification of the slot allocation procedure in dependence on the linefill slot occupancy criterion and is responsive to the linefill slot occupancy criterion being fulfilled to cause a linefill delegation action to be instructed to the level M cache level.
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Patent Agency Ranking
公开(公告)号：US20250021302A1
公开(公告)日：2025-01-16
申请号：US18763457
申请日：2024-07-03
Applicant: Arm Limited
Inventor： Olof Henrik Uhrenholt
Abstract: Disclosed is a method of evaluating trigonometric functions in floating point arithmetic. In particular, a range reduction operation is performed to reduce the input argument x into a desired reduced ranges of values within which the trigonometric function is to be evaluated. The range reduction involves a step of computing the product of the input argument x and R, wherein R is an approximation to m/pi (with m=2, for example). The value for R is obtained as a sum of terms R0+R1+ . . . and the value of the first term R0 is configured to ensure that the expression xR0 modulo 4 can be evaluated without floating point rounding error. This can then provide an improved graphics processor operation.
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公开(公告)号：US20250004767A1
公开(公告)日：2025-01-02
申请号：US18345164
申请日：2023-06-30
Applicant: Arm Limited
IPC: G06F9/30
Abstract: Mode change detection circuitry detects a mode change when processing circuitry switches between first and second modes of processing in which a first set of architectural registers are designated as having different register lengths. Register mapping circuitry maps architectural registers to corresponding physical registers. For an operation specifying a given architectural register of the first set of architectural registers: in response to a determination that the operation is to be processed in the first mode of processing, the register mapping circuitry maps the given architectural register to a physical register of a first physical register file, and in response to a determination that the operation is to be processed in the second mode of processing, the register mapping circuitry maps the given architectural register to a physical register of a second physical register file separate from the first physical register file and having physical registers of different register length to physical registers of the first physical register file.
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公开(公告)号：US12182575B2
公开(公告)日：2024-12-31
申请号：US18079308
申请日：2022-12-12
Applicant: Arm Limited
Inventor： Mbou Eyole
IPC: G06F9/38
Abstract: A data processing apparatus comprises: a physical register array, prediction circuitry, register rename circuitry, and hardware execution circuitry. The physical register array comprises a plurality of sectors having one or more different access properties, each of the plurality of sectors having one or more different access properties compared to other sectors of the plurality of sectors, each sector of the plurality of sectors comprising at least one physical register. The prediction circuitry to predict, for a given instruction, a sector identifier identifying one of the sectors of the physical register array to be used for a destination register of the given instruction. The prediction circuitry is configured to select the sector identifier in dependence on prediction information learnt from performance monitoring information indicative of performance achieved for a sequence of instructions when using different sector identifiers for the given instruction. The register rename circuitry to map a destination architectural register identifier specified by the given instruction to a destination physical register in the sector identified by the sector identifier predicted by the prediction circuitry. The execution circuitry to execute the given instruction and generate a result to be written to the destination physical register mapped to the destination architectural register identifier by the register rename circuitry.
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公开(公告)号：US12182427B2
公开(公告)日：2024-12-31
申请号：US17966071
申请日：2022-10-14
Applicant: Arm Limited
Inventor： Stefano Ghiggini , Natalya Bondarenko , Luca Nassi , Geoffray Matthieu Lacourba , Huzefa Moiz Sanjeliwala , Miles Robert Dooley , Abhishek Raja
IPC: G06F3/06
Abstract: An apparatus is provided for controlling the operating mode of control circuitry, such that the control circuitry may change between two operating modes. In an allocation mode, data that is loaded in response to an instruction is allocated into storage circuitry from an intermediate buffer, and the data is read from the storage circuitry. In a non-allocation mode, the data is not allocated to the storage circuitry, and is read directly from intermediate buffer. The control of the operating mode may be performed by mode control circuitry, and the mode may be changed in dependence on the type of instruction that calls the data, and whether the data may be used again in the near future, or whether it is expected to be used only once.
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公开(公告)号：US12176904B2
公开(公告)日：2024-12-24
申请号：US17501642
申请日：2021-10-14
Applicant: Arm Limited
Inventor： Shashank Guruprasad , Roma Rudra , Mikael Yves Marie Rien , Karthik Sankaranarayanan
Abstract: According to one implementation of the present disclosure, a circuit includes: two or more metal wires, respective XOR gates coupled to each of the two or more top metal wires, a shift register having outputs coupled to the XOR gates, an OR gate configured to receive each of the outputs of the XOR gates, and a latch configured to receive an output of the OR gate and transmit an output signal corresponding to an alarm signal.
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