公开(公告)号：US08552508B2

公开(公告)日：2013-10-08

申请号：US12754129

申请日：2010-04-05

申请人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

发明人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC分类号： H01L27/088

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Gate electrodes are formed from conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The gate electrodes include gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are substantially equal, such that the first and second PMOS transistor devices have substantially equal widths. Widths of the first and second n-type diffusion regions are substantially equal, such that the first and second NMOS transistor devices have substantially equal widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration.

摘要翻译： 半导体器件包括第一和第二p型扩散区，以及第一和第二n型扩散区，其各自电连接到公共节点。 栅极电极由导电特征形成，每个导电特征各自限定在与多个平行栅极电极轨道中的一个唯一相关联并限定的任何一个栅极电平通道内。 栅电极包括第一和第二PMOS晶体管器件的栅电极以及第一和第二NMOS晶体管器件。 第一和第二p型扩散区域的宽度基本相等，使得第一和第二PMOS晶体管器件具有基本相等的宽度。 第一和第二n型扩散区域的宽度基本相等，使得第一和第二NMOS晶体管器件具有基本相等的宽度。 第一和第二PMOS和第一和第二NMOS晶体管器件形成交叉耦合晶体管配置。

公开(公告)号：US20130214361A1

公开(公告)日：2013-08-22

申请号：US13591141

申请日：2012-08-21

申请人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

发明人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC分类号： H01L27/092 ,  G06F17/50

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

摘要翻译： 半导体器件包括导电特征，每个导电特征各自被限定在与多个平行栅极电极轨道中的一个唯一相关联并限定的任何一个栅极电平通道内。 导电特征形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一PMOS和第一NMOS晶体管器件的栅电极沿着第一栅电极轨道延伸。 第二PMOS和第二NMOS晶体管器件的栅电极沿着第二栅极电极延伸。 第一组互连导体电连接第一PMOS和第二NMOS晶体管器件的栅电极。 第二组互连导体电连接第二PMOS和第一NMOS晶体管器件的栅电极。 第一组和第二组互连导体在半导体器件的不同级别内横越彼此。

公开(公告)号：US20130207196A1

公开(公告)日：2013-08-15

申请号：US13831636

申请日：2013-03-15

申请人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

发明人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC分类号： H01L27/092

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a third gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a fourth gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

摘要翻译： 第一PMOS晶体管由沿着第一栅电极轨延伸的栅电极限定。 第二PMOS晶体管由沿着第二栅电极轨道延伸的栅电极限定。 第一NMOS晶体管由沿着第三栅电极轨道延伸的栅电极限定。 第二NMOS晶体管由沿着第四栅电极轨道延伸的栅电极限定。 第一PMOS晶体管和第一NMOS晶体管的栅极电连接到第一栅极节点。 第二PMOS晶体管和第二NMOS晶体管的栅极电连接到第二栅极节点。 第一PMOS晶体管，第一NMOS晶体管，第二PMOS晶体管和第二NMOS晶体管中的每一个具有电连接到公共输出节点的相应扩散端。

公开(公告)号：US20130200469A1

公开(公告)日：2013-08-08

申请号：US13831811

申请日：2013-03-15

申请人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

发明人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC分类号： H01L27/088 ,  G06F17/50

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.

摘要翻译： 第一栅极电平特征形成第一晶体管类型的第一晶体管和第二晶体管类型的第一晶体管的栅电极。 第二栅极电平特征形成第一晶体管类型的第二晶体管的栅电极。 第三栅极电平特征形成第二晶体管类型的第二晶体管的栅电极。 第一和第二晶体管类型的第二晶体管的栅电极彼此电连接。 第一和第二晶体管类型的第二晶体管的栅电极位于第一和第二晶体管类型的第一晶体管的栅电极所位于的栅电极轨道的相对侧上。

公开(公告)号：US20130200463A1

公开(公告)日：2013-08-08

申请号：US13831530

申请日：2013-03-14

申请人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

发明人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC分类号： H01L27/092

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a second gate electrode track. A second PMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along the first gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

摘要翻译： 第一PMOS晶体管由沿着第一栅电极轨延伸的栅电极限定。 第一NMOS晶体管由沿着第二栅电极轨道延伸的栅电极限定。 第二PMOS晶体管由沿着第二栅极电极延伸的栅电极限定。 第二NMOS晶体管由沿着第一栅电极轨道延伸的栅电极限定。 第一PMOS晶体管和第一NMOS晶体管的栅极电连接到第一栅极节点。 第二PMOS晶体管和第二NMOS晶体管的栅极电连接到第二栅极节点。 第一PMOS晶体管，第一NMOS晶体管，第二PMOS晶体管和第二NMOS晶体管中的每一个具有电连接到公共输出节点的相应扩散端。

公开(公告)号：US08453094B2

公开(公告)日：2013-05-28

申请号：US12363705

申请日：2009-01-30

申请人： Stephen Kornachuk ,  Jim Mali ,  Carole Lambert ,  Scott T. Becker

发明人： Stephen Kornachuk ,  Jim Mali ,  Carole Lambert ,  Scott T. Becker

IPC分类号： G06F17/50

CPC分类号： H01L23/528 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/12 ,  H01L23/498 ,  H01L23/5283 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

公开(公告)号：US20130126978A1

公开(公告)日：2013-05-23

申请号：US13740191

申请日：2013-01-12

申请人： Scott T. Becker ,  Michael C. Smayling ,  Dhrumil Gandhi ,  Jim Mali ,  Carole Lambert ,  Jonathan R. Quandt ,  Daryl Fox

发明人： Scott T. Becker ,  Michael C. Smayling ,  Dhrumil Gandhi ,  Jim Mali ,  Carole Lambert ,  Jonathan R. Quandt ,  Daryl Fox

IPC分类号： H01L27/092 ,  G06F17/50 ,  H01L21/36

CPC分类号： H01L27/0886 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/02521 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/7853 ,  Y02P90/265

摘要： A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.

摘要翻译： 第一晶体管具有在第一扩散鳍内的源区和漏区。 第一扩散鳍片从衬底的表面突出。 第一扩散鳍从第一扩散翅片的第一端到第二端在第一方向上纵向延伸。 第二晶体管具有在第二扩散鳍内的源区和漏区。 第二扩散鳍片从衬底的表面突出。 第二扩散翅片在第一方向上从第二扩散鳍片的第一端部延伸到第二端部的纵向延伸。 第二扩散翅片位于第一扩散鳍的旁边并与之隔开。 第二扩散翅片的第一端或第二端都位于第一扩散鳍片的第一端和第二端之间的第一方向上。

公开(公告)号：US20090228857A1

公开(公告)日：2009-09-10

申请号：US12363705

申请日：2009-01-30

申请人： Stephen Kornachuk ,  Jim Mali ,  Carole Lambert

发明人： Stephen Kornachuk ,  Jim Mali ,  Carole Lambert

IPC分类号： G06F17/50

CPC分类号： H01L23/528 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/12 ,  H01L23/498 ,  H01L23/5283 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

摘要翻译： 为芯片级定义全局放置光栅（GPG），以包括一组平行和均匀间隔的虚拟线。 GPG的至少一个虚拟线被定位成与与芯片级连接的每个触点相交。 定义了一些子格局。 每个子格局是GPG的一组等间距虚拟线，其支撑在其上的公共布局形状游程长度。 芯片级的布局被划分为子格局。 每个子格局区域具有分配给其中的任何一个限定的子格局。 放置在芯片级别的给定子格局区域内的布局形状根据分配给给定亚格局区域的子格局放置。 通过布局形状拉伸，布局形状插入和/或子分解形状插入可以减轻亚格子区域边界处的非标准布局形状间隔，或者可以允许存在于最终布局中。

公开(公告)号：US10651200B2

公开(公告)日：2020-05-12

申请号：US13831605

申请日：2013-03-15

申请人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

发明人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC分类号： H01L27/088 ,  H01L27/118 ,  H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  H01L27/02 ,  H01L27/092 ,  G06F17/50 ,  H01L23/538 ,  H01L23/498 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/105

摘要： A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

公开(公告)号：US10020321B2

公开(公告)日：2018-07-10

申请号：US13831530

申请日：2013-03-14

申请人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

发明人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC分类号： H01L27/11 ,  H01L27/092 ,  H01L27/118 ,  G11C11/412 ,  G11C5/06 ,  H01L27/02 ,  G06F17/50 ,  H01L27/088 ,  H01L23/538 ,  H01L23/498 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/105

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a second gate electrode track. A second PMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along the first gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.