公开(公告)号：US20110047309A1

公开(公告)日：2011-02-24

申请号：US12937685

申请日：2008-04-28

Applicant: Hubert E. Brinkmann ,  Paul V. Brownell ,  David L. Mattews ,  Dwight D. Riley

Inventor： Hubert E. Brinkmann ,  Paul V. Brownell ,  David L. Mattews ,  Dwight D. Riley

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F9/45558 ,  G06F2009/45579 ,  G06F2213/0026

Abstract: Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.

Abstract translation: 本发明的实施例涉及用于代表包括I / O设备控制器的中断产生设备虚拟化中断模式的方法，使得缺少较旧的中断模式的较新的中断产生设备可以在继续依赖的系统中使用 在较老的中断模式下。 在本发明的一个实施例中，改进了PCIe交换机或基于PCIe的主桥，或者引入了新的组件来提供代表虚拟中断模式的中断模式虚拟化功能或虚拟中断模式接口 诸如I / O设备控制器的中断产生设备到操作系统，BIOS层以及与I / O设备控制器通信的其他组件。

公开(公告)号：US07876759B2

公开(公告)日：2011-01-25

申请号：US11775967

申请日：2007-07-11

Applicant: Hahn Vo Norden ,  Hubert E. Brinkmann ,  Paul V. Brownell ,  Kenneth T. Chin ,  James Dinh ,  David L. Matthews ,  Dwight D. Riley

Inventor： Hahn Vo Norden ,  Hubert E. Brinkmann ,  Paul V. Brownell ,  Kenneth T. Chin ,  James Dinh ,  David L. Matthews ,  Dwight D. Riley

IPC: H04L12/56

CPC classification number: H04L47/10 ,  H04L47/32 ,  H04L47/39

Abstract: A system is provided comprising a fabric coupling together a plurality of computing devices, wherein the fabric transfers a stream of packets between the computing devices. Each computing device comprises a Quality of Service (“QOS”) filter that monitors incoming packets to filter out packets of a maintenance type and permit transfer of packets of a transaction type.

Abstract translation: 提供了一种系统，其包括将多个计算设备耦合在一起的结构，其中该结构在计算设备之间传送分组流。 每个计算设备包括服务质量（“QOS”）过滤器，其监视进入的分组以过滤维护类型的分组并且允许传输交易类型的分组。

公开(公告)号：US07110413B2

公开(公告)日：2006-09-19

申请号：US10038793

申请日：2001-12-31

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: H04L12/28

CPC classification number: H04L12/46 ,  H04L12/4625

Abstract: An interconnect switch provides full PCI compatibility while increasing performance via concurrency. The switch contains a primary bridge on a primary port. Secondary ports of the switch can be connected to secondary bridges and end devices. The switch can shadow registers associated with the secondary bridges. A transaction with a target address behind a secondary bridge is directly routed to the secondary port associated with the secondary bridge, using the shadowed registers. A transaction with a target address not behind a secondary bridge is routed to each of the other secondary ports. The transaction can be broadcast to all of the non-bridge secondary ports or can be routed successively to each of the non-bridge secondary ports until accepted. A tuning process can use positive acknowledgment of a transaction by an end device connected to a secondary port to directly route similar transactions to the same secondary port.

公开(公告)号：US07093146B2

公开(公告)日：2006-08-15

申请号：US10210424

申请日：2002-07-31

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: G06F1/32

CPC classification number: G06F1/3215 ,  G06F1/26

Abstract: A distributed power management technique allows controlling power states of devices separated from a power management controller, such as a processor, by an interconnect. The power management controller inserts power state information into an interconnect transaction. An interconnect connected device then extracts the power state information and modifies the power state of the device responsive to the power state information. The power state information can be extracted by a processor that then controls the power state of another device responsive to the power state information.

Abstract translation: 分布式电力管理技术允许通过互连来控制与诸如处理器的电力管理控制器分离的设备的电力状态。 电源管理控制器将电源状态信息插入互连事务。 然后，互连连接设备提取功率状态信息，并根据功率状态信息修改设备的功率状态。 功率状态信息可以由处理器提取，然后处理器响应于功率状态信息来控制另一设备的功率状态。

公开(公告)号：US07028132B2

公开(公告)日：2006-04-11

申请号：US09967607

申请日：2001-09-29

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: G06F13/36

CPC classification number: G06F13/423

Abstract: Distributed peer-to-peer transactions are defined on an interconnect bus of a computer system according to an interconnect protocol. The transactions contain a completer device attribute data and a self-defining payload data. The transaction is identified as a peer-to-peer transaction by a command or an attribute data in the transaction. The transaction can be routed across a hierarchy of interconnect bus segments using the completer device address data. A handle can be used by an operating system of the computer system to indicate permission for the peer-to-peer transaction. Address information in a completer device address space can be provided within the peer-to-peer transaction or by a completer device driver for use by the completer device in processing the peer-to-peer transaction.

公开(公告)号：US6088517A

公开(公告)日：2000-07-11

申请号：US950297

申请日：1997-10-14

Applicant: Christopher C. Wanner ,  Jeffrey C. Stevens ,  Robert A. Lester ,  Dwight D. Riley ,  David J. Maguire ,  James Edwards

Inventor： Christopher C. Wanner ,  Jeffrey C. Stevens ,  Robert A. Lester ,  Dwight D. Riley ,  David J. Maguire ,  James Edwards

IPC: G06F13/12 ,  G06F13/28 ,  G06F13/00

CPC classification number: G06F13/28 ,  G06F13/126

Abstract: A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

Abstract translation: 计算机系统在总线上具有单独的，但兼容的DMA控制器。 用于控制至少一个DMA通道的每个DMA控制器，每个DMA控制器具有用于执行DMA操作的独立的一组寄存器和用于指示通道状态和指定的配置寄存器。 DMA主机，用于与处理器进行兼容通信，并与多个DMA控制器进行初始化和通信。

公开(公告)号：US5864688A

公开(公告)日：1999-01-26

申请号：US684584

申请日：1996-07-19

Applicant: Gregory N. Santos ,  David J. Maguire ,  Dwight D. Riley ,  James R. Edwards

Inventor： Gregory N. Santos ,  David J. Maguire ,  Dwight D. Riley ,  James R. Edwards

IPC: G06F13/36 ,  G06F13/40 ,  G06F12/00

CPC classification number: G06F13/4045

Abstract: A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

Abstract translation: 具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。 扩展基座和便携式部分都包括用于将周期从外围部件互连（PCI）总线传递到工业标准架构（ISA）总线的桥接电路。 该桥包括用于控制解码的内部设备和配置寄存器。 用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。 根据对接状态，由桥接电路之一对其中一个电路进行正确解码和声明的循环进行减法解码。

公开(公告)号：US5781748A

公开(公告)日：1998-07-14

申请号：US671316

申请日：1996-07-19

Applicant: Gregory N. Santos ,  David J. Maguire ,  Dwight D. Riley ,  James R. Edwards

Inventor： Gregory N. Santos ,  David J. Maguire ,  Dwight D. Riley ,  James R. Edwards

IPC: G06F13/40 ,  H01J13/00

CPC classification number: G06F13/4027

Abstract: A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

Abstract translation: 具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。 扩展基座和便携式部分都包括用于将周期从外围部件互连（PCI）总线传递到工业标准架构（ISA）总线的桥接电路。 该桥包括用于控制解码的内部设备和配置寄存器。 用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。 根据对接状态，由桥接电路之一对其中一个电路进行正确解码和声明的循环进行减法解码。

公开(公告)号：US08464260B2

公开(公告)日：2013-06-11

申请号：US11930854

申请日：2007-10-31

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: G06F9/48 ,  G06F9/455 ,  G06F13/20

CPC classification number: G06F9/468 ,  G06F21/44 ,  G06F21/53 ,  G06F21/606

Abstract: A hardware device interface supporting transaction authentication is described herein. At least some illustrative embodiments include a device, including an interconnect interface, and processing logic (coupled to the bus interface) that provides access to a plurality of functions of the device through the interconnect interface. A first transaction received by the device, and associated with a function of the plurality of functions, causes a request identifier within the first transaction to be assigned to the function. Access to the function is denied if a request identifier of a second transaction, subsequent to the first transaction, does not match the request identifier assigned to the function.

Abstract translation: 本文描述了支持事务认证的硬件设备接口。 至少一些说明性实施例包括通过互连接口提供对设备的多个功能的访问的设备，包括互连接口和处理逻辑（耦合到总线接口）。 由设备接收并与多个功能的功能相关联的第一事务使第一事务中的请求标识符被分配给该功能。 如果在第一个事务之后的第二个事务的请求标识符与分配给该函数的请求标识符不匹配，则对该函数的访问被拒绝。

公开(公告)号：US08374175B2

公开(公告)日：2013-02-12

申请号：US11116008

申请日：2005-04-27

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: H04L12/50 ,  H04Q11/00 ,  G06F13/28

CPC classification number: H04L45/22 ,  H04L49/3036 ,  H04L49/35 ,  H04L49/552

Abstract: A system and method for remote direct memory access over a network switch fabric. Some illustrative embodiments may include a system comprising a first system node, a direct memory access (DMA) controller, a second system node, and a network switch fabric coupling together the first and second system nodes (the network switch fabric comprises a rooted hierarchical bus). The DMA controller is configured to perform a DMA transfer of data between the first and second system nodes across the network switch fabric. The data is formatted as one or more remote DMA (RDMA) protocol messages that are routed across the network switch fabric based on a bus end-device identifier corresponding to the second system node.

Abstract translation: 一种用于通过网络交换结构进行远程直接内存访问的系统和方法。 一些说明性实施例可以包括包括第一系统节点，直接存储器访问（DMA）控制器，第二系统节点和将第一和第二系统节点耦合在一起的网络交换结构的系统（网络交换机结构包括根分层总线 ）。 DMA控制器被配置为通过网络交换结构在第一和第二系统节点之间执行数据的DMA传输。 数据被格式化为基于与第二系统节点相对应的总线终端设备标识符通过网络交换结构路由的一个或多个远程DMA（RDMA）协议消息。