公开(公告)号：US08169002B2

公开(公告)日：2012-05-01

申请号：US12759012

申请日：2010-04-13

申请人： Edward Yi Chang ,  Chien-I Kuo ,  Heng-Tung Hsu

发明人： Edward Yi Chang ,  Chien-I Kuo ,  Heng-Tung Hsu

IPC分类号： H01L29/66 ,  H01L21/338

CPC分类号： H01L29/7787 ,  B82Y10/00 ,  H01L29/1029 ,  H01L29/15 ,  H01L29/66462 ,  H01L29/7783

摘要： A high electron mobility transistor includes a substrate, a buffer layer, a channel layer, a spacer layer, a schottky layer and a cap layer. The buffer layer is formed on the substrate. The channel layer is formed on the buffer layer, in which the channel layer comprises a superlattice structure formed with a plurality of indium gallium arsenide thin films alternately stacked with a plurality of indium arsenide thin films. The spacer layer is formed on the channel layer. The schottky layer is formed on the spacer layer. The cap layer is formed on the schottky layer.

摘要翻译： 高电子迁移率晶体管包括衬底，缓冲层，沟道层，间隔层，肖特基层和覆盖层。 缓冲层形成在基板上。 沟道层形成在缓冲层上，其中沟道层包括由多个砷化铟锡薄膜交替层叠的多个砷化铟镓薄膜形成的超晶格结构。 间隔层形成在沟道层上。 在间隔层上形成肖特基层。 盖层形成在肖特基层上。

公开(公告)号：US20110146779A1

公开(公告)日：2011-06-23

申请号：US12659955

申请日：2010-03-26

申请人： Edward Yi Chang ,  Kartika Chandra Sahoo ,  Men-Ku Lin ,  Yi-Yao Lu ,  Sheng-Ping Wang

发明人： Edward Yi Chang ,  Kartika Chandra Sahoo ,  Men-Ku Lin ,  Yi-Yao Lu ,  Sheng-Ping Wang

IPC分类号： H01L31/0224 ,  H01L31/18 ,  H01L31/0352

CPC分类号： H01L33/22 ,  H01L31/02168 ,  H01L31/0236 ,  Y02E10/50

摘要： The present invention relates to a method for fabricating a sub-wavelength structure layer, including: forming a metal film on a passivation layer, an n-GaN layer or a transparent conductive oxide layer; performing thermal treatment to form self assembled metal nano particles; using the metal nano particles as a mask to remove a partial area of the passivation layer, the n-GaN layer or the transparent conductive oxide layer to form a sub-wavelength structure of which the cross-sectional area increases along the thickness direction of the passivation layer, the n-GaN layer or the transparent conductive oxide layer; and removing the metal nano particles. In addition, the present invention further provides the obtained sub-wavelength structure layer and a photoelectric conversion device using the same.

摘要翻译： 本发明涉及一种制造亚波长结构层的方法，包括：在钝化层，n-GaN层或透明导电氧化物层上形成金属膜; 进行热处理以形成自组装的金属纳米颗粒; 使用金属纳米颗粒作为掩模去除钝化层，n-GaN层或透明导电氧化物层的部分区域，以形成沿着厚度方向的横截面积增加的亚波长结构 钝化层，n-GaN层或透明导电氧化物层; 并去除金属纳米颗粒。 此外，本发明还提供所获得的亚波长结构层和使用其的光电转换装置。

公开(公告)号：US07847410B2

公开(公告)日：2010-12-07

申请号：US11164404

申请日：2005-11-22

申请人： Cheng-Shih Lee ,  Edward Yi Chang ,  Huang-Choung Chang

发明人： Cheng-Shih Lee ,  Edward Yi Chang ,  Huang-Choung Chang

IPC分类号： H01L23/48

CPC分类号： H01L29/7371 ,  H01L23/53238 ,  H01L29/41708 ,  H01L29/41725 ,  H01L29/42304 ,  H01L29/66318 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect of the group III-V semiconductor device and the fabrication method for making the same are described. The interconnect includes a first adhesion layer, a diffusion barrier layer for preventing the copper from diffusing, a second adhesion layer and a copper wire line. Because a stacked-layer structure of the first adhesion layer/diffusion barrier layer/second adhesion layer is located between the copper wire line and the group III-V semiconductor device, the adhesion between the diffusion barrier layer and other materials is improved. Therefore, the yield of the device is increased.

摘要翻译： 描述了III-V族半导体器件的互连及其制造方法。 互连包括第一粘合层，用于防止铜扩散的扩散阻挡层，第二粘合层和铜线。 由于第一粘附层/扩散阻挡层/第二粘合层的堆叠层结构位于铜线和III-V族半导体器件之间，所以扩散阻挡层与其它材料之间的粘合性提高。 因此，装置的产量增加。

公开(公告)号：US20090194846A1

公开(公告)日：2009-08-06

申请号：US12025021

申请日：2008-02-02

申请人： Edward Yi CHANG ,  Ke-Shian Chen

发明人： Edward Yi CHANG ,  Ke-Shian Chen

IPC分类号： H01L29/732

CPC分类号： H01L29/7371 ,  H01L23/53238 ,  H01L29/452 ,  H01L29/475 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention discloses a fully Cu-metallized III-V group compound semiconductor device, wherein the fully Cu-metallized of a III-V group compound semiconductor device is realized via using an N-type gallium arsenide ohmic contact metal layer formed of a palladium/germanium/copper composite metal layer, a P-type gallium arsenide ohmic contact metal layer formed of a platinum/titanium/platinum/copper composite metal layer, and interconnect metals formed of a titanium/platinum/copper composite metal layer. Thereby, the fabrication cost of III-V group compound semiconductor devices can be greatly reduced, and the performance of III-V group compound semiconductor devices can be greatly promoted. Besides, the heat-dissipation effect can also be increased, and the electric impedance can also be reduced.

摘要翻译： 本发明公开了一种完全Cu金属化的III-V族化合物半导体器件，其中通过使用由钯形成的N型砷化镓欧姆接触金属层来实现III-V族化合物半导体器件的完全Cu金属化 /锗/铜复合金属层，由铂/钛/铂/铜复合金属层形成的P型砷化镓欧姆接触金属层和由钛/铂/铜复合金属层形成的互连金属。 因此，III-V族化合物半导体器件的制造成本可以大大降低，可以大大提高III-V族化合物半导体器件的性能。 此外，还可以提高散热效果，并且还可以降低电阻抗。

公开(公告)号：US20070040274A1

公开(公告)日：2007-02-22

申请号：US11164404

申请日：2005-11-22

申请人： Cheng-Shih Lee ,  Edward Yi Chang ,  Huang-Choung Chang

发明人： Cheng-Shih Lee ,  Edward Yi Chang ,  Huang-Choung Chang

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L29/7371 ,  H01L23/53238 ,  H01L29/41708 ,  H01L29/41725 ,  H01L29/42304 ,  H01L29/66318 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect of the group III-V semiconductor device and the fabrication method for making the same are described. The interconnect includes a first adhesion layer, a diffusion barrier layer for preventing the copper from diffusing, a second adhesion layer and a copper wire line. Because a stacked-layer structure of the first adhesion layer/diffusion barrier layer/second adhesion layer is located between the copper wire line and the group III-V semiconductor device, the adhesion between the diffusion barrier layer and other materials is improved. Therefore, the yield of the device is increased.

摘要翻译： 描述了III-V族半导体器件的互连及其制造方法。 互连包括第一粘合层，用于防止铜扩散的扩散阻挡层，第二粘合层和铜线。 由于第一粘附层/扩散阻挡层/第二粘合层的堆叠层结构位于铜线和III-V族半导体器件之间，所以扩散阻挡层与其它材料之间的粘附性得到改善。 因此，装置的产量增加。

公开(公告)号：US08736349B2

公开(公告)日：2014-05-27

申请号：US13596104

申请日：2012-08-28

申请人： Tsung-Lin Chen ,  Edward Yi Chang ,  Wei-Hua Chieng ,  Stone Cheng ,  Shyr-Long Jeng ,  Shin-Wei Huang

发明人： Tsung-Lin Chen ,  Edward Yi Chang ,  Wei-Hua Chieng ,  Stone Cheng ,  Shyr-Long Jeng ,  Shin-Wei Huang

IPC分类号： H03K17/687

CPC分类号： H03K17/163

摘要： The present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The source and the drain of the first transistor couple with the diode. The source of the second transistor couples with the gate of the first transistor. The source of the first transistor couples with the first transistor. The source of the second transistor couples with the second resistor. The third resistor couples with the fourth resistor and the gate of the first transistor. The first transistor turned off and the gate current is limited. When the current of the gate of the GaN transistor exceeds the predetermined value, the breakdown voltage is increased by limiting the gate current.

摘要翻译： 本发明提供一种与GaN晶体管的栅极耦合的限流电路装置。 电流限制电路包括二极管，第一晶体管，第二晶体管，第一电阻器，第二电阻器，第三电阻器和第四电阻器。 第一晶体管的源极和漏极与二极管耦合。 第二晶体管的源极与第一晶体管的栅极耦合。 第一晶体管的源极与第一晶体管耦合。 第二晶体管的源极与第二电阻耦合。 第三电阻器与第四电阻器和第一晶体管的栅极耦合。 第一晶体管截止，栅极电流受限。 当GaN晶体管的栅极的电流超过预定值时，通过限制栅极电流来增加击穿电压。

公开(公告)号：US20130241601A1

公开(公告)日：2013-09-19

申请号：US13596113

申请日：2012-08-28

申请人： Tsung-Lin CHEN ,  Edward Yi CHANG ,  Wei-Hua CHIENG ,  Stone CHENG ,  Shyr-Long JENG ,  Che-Wei CHANG

发明人： Tsung-Lin CHEN ,  Edward Yi CHANG ,  Wei-Hua CHIENG ,  Stone CHENG ,  Shyr-Long JENG ,  Che-Wei CHANG

IPC分类号： H03K3/00

CPC分类号： H03K17/063 ,  H03K2217/0063 ,  H03K2217/0081

摘要： The present invention provides a high-side driver circuit including a power transistor, the first transistor, the second transistor, the second capacitor, the second diode, a start-up circuit. The start-up circuit is coupled between a resistor and the second capacitor to complete a gate driving circuit. And, the aforementioned resistor can either be the gate resistance of the power transistor or an external resistor. The design of start-up circuit enables the functionality of the bootstrap capacitor of being charged to a designate voltage level. Thus, the depletion-mode transistor can be controlled to turn on/off without a floating voltage source or a negative voltage source.

公开(公告)号：US20130175537A1

公开(公告)日：2013-07-11

申请号：US13455527

申请日：2012-04-25

申请人： EDWARD YI CHANG ,  CHIA-HUA CHANG ,  YUEH-CHIN LIN ,  YU KONG CHEN ,  SHIH-CHIEN LIU

发明人： EDWARD YI CHANG ,  CHIA-HUA CHANG ,  YUEH-CHIN LIN ,  YU KONG CHEN ,  SHIH-CHIEN LIU

IPC分类号： H01L29/20

CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/452 ,  H01L29/7787

摘要： A high electron mobility GaN-based transistor structure comprises a substrate, an epitaxial GaN layer formed on the substrate, at least one ohmic contact layer formed on the epitaxial GaN layer, a metallic gate layer formed on the epitaxial GaN layer, and a diffusion barrier layer interposed between the metallic gate layer and the epitaxial GaN layer. The diffusion barrier layer hinders metallic atoms of the metallic gate layer from diffusing into the epitaxial GaN layer, whereby are improved the electric characteristics and reliability of the GaN-based transistor.

摘要翻译： 高电子迁移率GaN基晶体管结构包括衬底，在衬底上形成的外延GaN层，形成在外延GaN层上的至少一个欧姆接触层，形成在外延GaN层上的金属栅极层和扩散阻挡层 介于金属栅极层和外延GaN层之间的层。 扩散阻挡层阻碍金属栅极层的金属原子扩散到外延GaN层中，从而提高GaN基晶体管的电特性和可靠性。

公开(公告)号：US20130153886A1

公开(公告)日：2013-06-20

申请号：US13477868

申请日：2012-05-22

申请人： Edward Yi. Chang ,  Yueh-Chin Lin ,  Chia-Hua Chang ,  Hai-Dang Trinh

发明人： Edward Yi. Chang ,  Yueh-Chin Lin ,  Chia-Hua Chang ,  Hai-Dang Trinh

IPC分类号： H01L29/12 ,  H01L21/02

CPC分类号： H01L29/517 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02266 ,  H01L21/28264 ,  H01L29/78 ,  H01L29/94

摘要： The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a III-V semiconductor layer; an aluminum oxide layer formed on the III-V semiconductor layer; and a lanthanide oxide layer formed on the aluminum oxide layer. The method of manufacturing a semiconductor device includes: forming an aluminum oxide layer between a III-V semiconductor layer and a lanthanide oxide layer so as to prevent an inter-reaction of atoms between the III-V semiconductor layer and the lanthanide oxide layer.

摘要翻译： 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 半导体器件包括：III-V半导体层; 形成在III-V半导体层上的氧化铝层; 和在氧化铝层上形成的镧系元素氧化物层。 制造半导体器件的方法包括：在III-V半导体层和镧系元素氧化物层之间形成氧化铝层，以防止III-V族半导体层和镧系元素氧化物层之间的原子的相互反应。

公开(公告)号：US20120305991A1

公开(公告)日：2012-12-06

申请号：US13584897

申请日：2012-08-14

申请人： EDWARD YI CHANG ,  HENG-TUNG HSU

发明人： EDWARD YI CHANG ,  HENG-TUNG HSU

IPC分类号： H01L29/778

CPC分类号： H01L29/7787 ,  H01L27/085 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66462

摘要： A manufacturing method of a device having series-connected HEMTs is presented. Transistors are formed on a substrate and integratedly serial-connected as an integrated device by interconnection wires. Therefore, the voltage of the device is the sum of the voltages across each transistors so that the device can have high breakdown voltage.