公开(公告)号：US08664111B2

公开(公告)日：2014-03-04

申请号：US13249505

申请日：2011-09-30

Applicant: Ha-Jin Lim ,  Moon-Han Park ,  Eun-Gon Kim ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

Inventor： Ha-Jin Lim ,  Moon-Han Park ,  Eun-Gon Kim ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

IPC: H01L21/4763

CPC classification number: H01L21/28123 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/517 ,  H01L29/518

Abstract: There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.

Abstract translation: 提供了制造半导体器件的方法。 在该方法中，在基板上形成包括高k电介质材料的栅极绝缘层。 在栅绝缘层上形成蚀刻停止层。 在蚀刻停止层上形成金属层。 在金属层上形成包括非晶硅的硬掩模。 使用硬掩模作为蚀刻掩模对金属层进行图案化以形成金属层图案。

公开(公告)号：US08252674B2

公开(公告)日：2012-08-28

申请号：US13195935

申请日：2011-08-02

Applicant: Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

Inventor： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

IPC: H01L21/3205

CPC classification number: H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

Abstract: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

Abstract translation: 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜 在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

公开(公告)号：US07973309B2

公开(公告)日：2011-07-05

申请号：US12435161

申请日：2009-05-04

Applicant: Tae-Gyun Kim ,  Dong-Suk Shin ,  Joo-Won Lee ,  Ha-Jin Lim

Inventor： Tae-Gyun Kim ,  Dong-Suk Shin ,  Joo-Won Lee ,  Ha-Jin Lim

IPC: H01L23/544

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer.

Abstract translation: 提供了用于检测器件隔离层中的空隙的测试元件组（TEG）图案。 TEG图案包括彼此平行并在第一方向上延伸的有源区域，分离有源区域的器件隔离层，跨过器件隔离层形成的第一接触和接触的第一有源区域 器件隔离层的表面，以及跨过器件隔离层形成的第二接触和接触器件隔离层的另一表面的第二有源区。

公开(公告)号：US20100167533A1

公开(公告)日：2010-07-01

申请号：US12647806

申请日：2009-12-28

Applicant: Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

Inventor： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

IPC: H01L21/3205

CPC classification number: H01L21/28518 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

Abstract: A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.

Abstract translation: 制造半导体集成电路（IC）器件的方法可以包括在衬底上的晶体管的至少一部分上形成第一硅化物层，在第一硅化物层中形成氮以形成第二硅化物层，形成第一应力层 在其上形成有晶体管的衬底上具有拉伸应力，并且用紫外线（UV）光照射第一应力层以形成具有比第一应力层更大的拉伸应力的第二应力层。

公开(公告)号：US20090291568A1

公开(公告)日：2009-11-26

申请号：US12385287

申请日：2009-04-03

Applicant: Ha-Jin Lim ,  Hyung-Suk Jung ,  Yun-Ki Choi

Inventor： Ha-Jin Lim ,  Hyung-Suk Jung ,  Yun-Ki Choi

IPC: H01L21/31

CPC classification number: H01L29/02 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28194 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517

Abstract: Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer.

Abstract translation: 提供半导体器件和形成半导体器件的方法，所述半导体器件包括在衬底上的第一介电层和第一介电层上的第二电介质层。 第一电介质层的碳浓度低于第二电介质层。

公开(公告)号：US20090283764A1

公开(公告)日：2009-11-19

申请号：US12435161

申请日：2009-05-04

Applicant: Tae-Gyun Kim ,  Dong-Suk Shin ,  Joo-Won Lee ,  Ha-Jin Lim

Inventor： Tae-Gyun Kim ,  Dong-Suk Shin ,  Joo-Won Lee ,  Ha-Jin Lim

IPC: H01L23/544

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer.

Abstract translation: 提供了用于检测器件隔离层中的空隙的测试元件组（TEG）图案。 TEG图案包括彼此平行并在第一方向上延伸的有源区域，分离有源区域的器件隔离层，跨过器件隔离层形成的第一接触和接触的第一有源区域 器件隔离层的表面，以及跨过器件隔离层形成的第二接触和接触器件隔离层的另一表面的第二有源区。

公开(公告)号：US20070001241A1

公开(公告)日：2007-01-04

申请号：US11396702

申请日：2006-04-04

Applicant: Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Yun Kim ,  Min Kim

Inventor： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Yun Kim ,  Min Kim

IPC: H01L29/94

CPC classification number: H01L21/823807 ,  H01L21/823857

Abstract: A semiconductor device may include a semiconductor substrate having a first region and a second region. The nitrogen-incorporated active region may be formed within the first region. A first gate electrode may be formed on the nitrogen-incorporated active region. A first gate dielectric layer may be interposed between the nitrogen-incorporated active region and the first gate electrode. The first gate dielectric layer may include a first dielectric layer and a second dielectric layer. The second dielectric layer may be a nitrogen contained dielectric layer. A second gate electrode may be formed on the second region. A second gate dielectric layer may be interposed between the second region and the second gate electrode. The first gate dielectric layer may have the same or substantially the same thickness as the second gate dielectric layer, and the nitrogen contained dielectric layer may contact with the nitrogen-incorporated active region.

Abstract translation: 半导体器件可以包括具有第一区域和第二区域的半导体衬底。 可以在第一区域内形成含氮的有源区。 可以在引入氮的有源区上形成第一栅电极。 第一栅极电介质层可插入在引入氮的有源区和第一栅电极之间。 第一栅介质层可以包括第一介电层和第二介电层。 第二电介质层可以是含氮介电层。 第二栅极电极可以形成在第二区域上。 可以在第二区域和第二栅电极之间插入第二栅极电介质层。 第一栅极介电层可以具有与第二栅极介电层相同或基本相同的厚度，并且含氮介电层可以与引入氮的有源区接触。

公开(公告)号：US08951853B1

公开(公告)日：2015-02-10

申请号：US12659474

申请日：2010-03-10

Applicant: Pan-Kwi Park ,  Dong-Suk Shin ,  Yong-Kuk Jeong ,  Dong-Hyun Roh ,  Ha-Jin Lim

Inventor： Pan-Kwi Park ,  Dong-Suk Shin ,  Yong-Kuk Jeong ,  Dong-Hyun Roh ,  Ha-Jin Lim

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7847

Abstract: A method of forming a semiconductor device includes forming a gate electrode and source/drain regions in a semiconductor substrate, forming a first capping nitride layer covering the gate electrode and the source/drain regions, the first capping nitride layer including a Si—H rich SiN layer, annealing the semiconductor substrate having the first capping nitride layer, and removing the first capping nitride layer.

Abstract translation: 形成半导体器件的方法包括在半导体衬底中形成栅电极和源/漏区，形成覆盖栅电极和源/漏区的第一覆盖氮化物层，第一覆盖氮化物层包括富Si-H SiN层，退火具有第一覆盖氮化物层的半导体衬底，以及去除第一覆盖氮化物层。

公开(公告)号：US08557713B2

公开(公告)日：2013-10-15

申请号：US12385287

申请日：2009-04-03

Applicant: Ha-Jin Lim ,  Hyung-Suk Jung ,  Yun-Ki Choi

Inventor： Ha-Jin Lim ,  Hyung-Suk Jung ,  Yun-Ki Choi

IPC: H01L21/31

CPC classification number: H01L29/02 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28194 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517

Abstract: Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer.

公开(公告)号：US08502286B2

公开(公告)日：2013-08-06

申请号：US12841245

申请日：2010-07-22

Applicant: Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park

Inventor： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park

IPC: H01L29/76

CPC classification number: H01L29/76 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/7843

Abstract: A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress.

Abstract translation: 半导体器件包括MOSFET和设置在MOSFET上的多个应力层，其中应力层包括设置在MOSFET上的第一应力层和设置在第一应力层上的第二应力层，第一应力层具有第一应力层 应力和第二应力层具有第二应力，并且第一应力不同于第二应力。