公开(公告)号：US20100167533A1

公开(公告)日：2010-07-01

申请号：US12647806

申请日：2009-12-28

申请人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

发明人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

摘要： A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.

摘要翻译： 制造半导体集成电路（IC）器件的方法可以包括在衬底上的晶体管的至少一部分上形成第一硅化物层，在第一硅化物层中形成氮以形成第二硅化物层，形成第一应力层 在其上形成有晶体管的衬底上具有拉伸应力，并且用紫外线（UV）光照射第一应力层以形成具有比第一应力层更大的拉伸应力的第二应力层。

公开(公告)号：US08227308B2

公开(公告)日：2012-07-24

申请号：US12647806

申请日：2009-12-28

申请人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

发明人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

IPC分类号： H01L21/8238

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

摘要： A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.

摘要翻译： 制造半导体集成电路（IC）器件的方法可以包括在衬底上的晶体管的至少一部分上形成第一硅化物层，在第一硅化物层中形成氮以形成第二硅化物层，形成第一应力层 在其上形成有晶体管的衬底上具有拉伸应力，并且用紫外线（UV）光照射第一应力层以形成具有比第一应力层更大的拉伸应力的第二应力层。

公开(公告)号：US20110018044A1

公开(公告)日：2011-01-27

申请号：US12841245

申请日：2010-07-22

申请人： HA-JIN LIM ,  Pan-Kwi Park ,  Dong-Suk Shin

发明人： HA-JIN LIM ,  Pan-Kwi Park ,  Dong-Suk Shin

IPC分类号： H01L29/78 ,  H01L29/94 ,  H01L27/092 ,  H01L21/31

CPC分类号： H01L29/76 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/7843

摘要： A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress.

摘要翻译： 半导体器件包括MOSFET和设置在MOSFET上的多个应力层，其中应力层包括设置在MOSFET上的第一应力层和设置在第一应力层上的第二应力层，第一应力层具有第一应力层 应力和第二应力层具有第二应力，并且第一应力不同于第二应力。

公开(公告)号：US20100171182A1

公开(公告)日：2010-07-08

申请号：US12652426

申请日：2010-01-05

申请人： Dong-Suk Shin ,  Pan-Kwi Park ,  Ha-Jin Lim ,  Joo-Chan Kim

发明人： Dong-Suk Shin ,  Pan-Kwi Park ,  Ha-Jin Lim ,  Joo-Chan Kim

IPC分类号： H01L27/092 ,  H01L21/3115

CPC分类号： H01L21/823412 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843

摘要： A strained semiconductor device includes a first plurality of transistors spaced with a first gate pitch, a second plurality of transistors spaced with a second gate pitch greater than the first gate pitch, and an etch stop layer disposed on the first and second pluralities of transistors. The etch stop layer between each of the second plurality of transistors has a greater proportion of a stress-altering material than the etch stop layer between each of the first plurality of transistors.

摘要翻译： 应变半导体器件包括与第一栅极间隔开的第一多个晶体管，与第一栅极间距大于第二栅极间隔的第二多个晶体管，以及设置在第一和第二多个晶体管上的蚀刻停止层。 第二多个晶体管中的每一个之间的蚀刻停止层具有比在第一多个晶体管中的每一个之间的蚀刻停止层更大的应力改变材料的比例。

公开(公告)号：US08951853B1

公开(公告)日：2015-02-10

申请号：US12659474

申请日：2010-03-10

申请人： Pan-Kwi Park ,  Dong-Suk Shin ,  Yong-Kuk Jeong ,  Dong-Hyun Roh ,  Ha-Jin Lim

发明人： Pan-Kwi Park ,  Dong-Suk Shin ,  Yong-Kuk Jeong ,  Dong-Hyun Roh ,  Ha-Jin Lim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7847

摘要： A method of forming a semiconductor device includes forming a gate electrode and source/drain regions in a semiconductor substrate, forming a first capping nitride layer covering the gate electrode and the source/drain regions, the first capping nitride layer including a Si—H rich SiN layer, annealing the semiconductor substrate having the first capping nitride layer, and removing the first capping nitride layer.

摘要翻译： 形成半导体器件的方法包括在半导体衬底中形成栅电极和源/漏区，形成覆盖栅电极和源/漏区的第一覆盖氮化物层，第一覆盖氮化物层包括富Si-H SiN层，退火具有第一覆盖氮化物层的半导体衬底，以及去除第一覆盖氮化物层。

公开(公告)号：US08502286B2

公开(公告)日：2013-08-06

申请号：US12841245

申请日：2010-07-22

申请人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park

发明人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park

IPC分类号： H01L29/76

CPC分类号： H01L29/76 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/7843

摘要： A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress.

摘要翻译： 半导体器件包括MOSFET和设置在MOSFET上的多个应力层，其中应力层包括设置在MOSFET上的第一应力层和设置在第一应力层上的第二应力层，第一应力层具有第一应力层 应力和第二应力层具有第二应力，并且第一应力不同于第二应力。

公开(公告)号：US09583592B2

公开(公告)日：2017-02-28

申请号：US14697266

申请日：2015-04-27

申请人： Pan-Kwi Park ,  Dong-Suk Shin ,  Seok-Jun Won ,  Weon-Hong Kim ,  Jae-Gon Lee

发明人： Pan-Kwi Park ,  Dong-Suk Shin ,  Seok-Jun Won ,  Weon-Hong Kim ,  Jae-Gon Lee

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/8234

CPC分类号： H01L29/66545 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02332 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover the dummy gate structure. A nitridation process is performed on the first spacer layer. An upper portion of the substrate adjacent to the dummy gate structure is removed to form a trench. An inner wall of the trench is cleaned. An epitaxial layer is formed to fill the trench. The dummy gate structure is replaced with a gate structure.

摘要翻译： 在制造半导体器件的方法中，在基板上形成虚拟栅极结构。 在衬底上形成第一间隔层以覆盖虚拟栅极结构。 在第一间隔层上进行氮化处理。 去除与伪栅极结构相邻的衬底的上部以形成沟槽。 清洁沟槽的内壁。 形成外延层以填充沟槽。 虚拟栅极结构被栅极结构代替。

公开(公告)号：US20130320434A1

公开(公告)日：2013-12-05

申请号：US13908440

申请日：2013-06-03

申请人： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

发明人： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

IPC分类号： H01L29/78

CPC分类号： H01L27/1104 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

摘要： In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

摘要翻译： 在半导体器件中，第一有源区具有第一西格玛形状，第二有源区具有第二西格玛形状。 当垂直于衬底并将第一栅电极的侧表面通过第一区域的线被定义为第一垂直线时，当垂直于衬底并通过第二栅电极的侧表面的线 在第二区域被定义为第二垂直线时，当第一垂直线和第一沟槽之间的最短距离被定义为第一水平距离时，并且当第二垂直线和第二沟槽之间的最短距离被定义为 第二水平距离，第一水平距离和第二水平距离之间的差等于或小于1nm。

公开(公告)号：US20160197188A1

公开(公告)日：2016-07-07

申请号：US15071502

申请日：2016-03-16

申请人： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

发明人： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

IPC分类号： H01L29/78 ,  H01L29/51 ,  H01L27/11 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165

CPC分类号： H01L27/1104 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

摘要： In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

公开(公告)号：US20160148930A1

公开(公告)日：2016-05-26

申请号：US15009276

申请日：2016-01-28

申请人： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

发明人： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC分类号： H01L27/088 ,  H01L29/10 ,  H01L27/02 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.