公开(公告)号：US20070133670A1

公开(公告)日：2007-06-14

申请号：US11635937

申请日：2006-12-08

Applicant: Kyu-Min Kang ,  Cheol-Ho Shin ,  Sung-Woo Choi ,  Sang-In Cho ,  Sang-Sung Choi ,  Kwang-Rob Park

Inventor： Kyu-Min Kang ,  Cheol-Ho Shin ,  Sung-Woo Choi ,  Sang-In Cho ,  Sang-Sung Choi ,  Kwang-Rob Park

IPC: H03H7/30

CPC classification number: H04L25/03038 ,  H04L2025/03439

Abstract: A parallel equalizer for a DS-CDMA UWB system and method thereof are provided. The parallel equalizer includes: a filter block for filtering a training input signal in a ‘training mode’, and filtering the plurality of input signals in parallel in a ‘symbol decision mode’; a symbol decision block for obtaining a symbol error based on a output from the filter block and a training symbol in the ‘training mode’, and estimating a transmission symbol for each of the input signals in the ‘symbol decision mode’, obtaining an error of one among the estimated transmission symbols for a symbol error calculating input signal; and an weight update block for updating a filter tap coefficients of the filter block based on the training input signal or the symbol error calculating input signal and the symbol error and transmitting the updated filter tap coefficients into the filter block.

Abstract translation: 提供了一种用于DS-CDMA UWB系统的并行均衡器及其方法。 并行均衡器包括：滤波器块，用于以“训练模式”对训练输入信号进行滤波，并且以“符号判定模式”并行地对多个输入信号进行滤波; 用于基于来自滤波块的输出和“训练模式”中的训练符号获得符号误差的符号判定块，并且以“符号判定模式”为每个输入信号估计发送符号，获得误差 估计的传输符号中的一个用于符号误差计算输入信号; 以及权重更新块，用于基于训练输入信号或符号误差计算输入信号和符号误差来更新滤波器块的滤波器抽头系数，并将更新的滤波器抽头系数发送到滤波器块。

公开(公告)号：US20070133662A1

公开(公告)日：2007-06-14

申请号：US11636049

申请日：2006-12-08

Applicant: Kyu-Min Kang ,  Sang-Sung Choi ,  Kwang-Roh Park ,  Sang-In Cho ,  Sung-Woo Choi ,  Chcol-Ho Shin

Inventor： Kyu-Min Kang ,  Sang-Sung Choi ,  Kwang-Roh Park ,  Sang-In Cho ,  Sung-Woo Choi ,  Chcol-Ho Shin

IPC: H04B1/00

CPC classification number: H04B1/709 ,  H04B1/707 ,  H04B1/7115 ,  H04B1/71637 ,  H04B1/7183

Abstract: A rake receiver for DS-CDMA UWB system and a DS-CDMA receiver having the same are provided. The rake receiver includes: a channel estimator for estimating a channel having a predetermined chip duration by using a synchronization acquisition sequence; a tracking module for detecting a channel variation and adjusting a synchronization position value when the channel variation is detected; a first switch for selecting one of an output value of an analog-to-digital converter and an output value of a correlator and outputting the selected value; a second switch for selecting one of the output value of the analog-to-digital converter and the output value of the correlator; and a plurality of demodulators having a parallel processing structure to demodulate received signals by using the channel estimation value inputted from the channel estimator, the synchronization position value stored by the tracking module, and an output value of the second switch.

Abstract translation: 提供了一种用于DS-CDMA UWB系统的瑞克接收机和具有该接收机的DS-CDMA接收机。 耙式接收机包括：信道估计器，用于通过使用同步获取序列来估计具有预定码片持续时间的信道; 跟踪模块，用于在检测到信道变化时检测信道变化并调整同步位置值; 用于选择模数转换器的输出值之一和相关器的输出值并输出所选值的第一开关; 用于选择模数转换器的输出值之一和相关器的输出值的第二开关; 以及具有并行处理结构的多个解调器，通过使用从信道估计器输入的信道估计值，由跟踪模块存储的同步位置值和第二开关的输出值来解调接收信号。

公开(公告)号：US20070058922A1

公开(公告)日：2007-03-15

申请号：US11449412

申请日：2006-06-08

Applicant: In Cho ,  Woo Lee ,  Seung Ahn ,  Sang Han

Inventor： In Cho ,  Woo Lee ,  Seung Ahn ,  Sang Han

IPC: G02B6/00

CPC classification number: G02B6/138 ,  G02B6/4203

Abstract: Provided are an optical waveguide master and a method of manufacturing the same, which has a 90° optical path change structure and an integrated optical waveguide with a 45° inclined reflection surface. The optical waveguide with the inclined reflection surface manufactured using the optical waveguide master facilitates coupling between the active optical electronic device and the waveguide, thereby perfectly overcoming difficulty in conventional mass production. The optical waveguide makes it possible to accomplish connection between various optical devices and optical circuits, and becomes source technology of an optical printed circuit board (PCB) and a system on package (SOP) in the future.

Abstract translation: 提供一种具有90°光路改变结构的光波导母及其制造方法，以及具有45°倾斜反射面的集成光波导。 使用光波导母盘制造的具有倾斜反射面的光波导有利于有源光电子器件与波导之间的耦合，从而完美地克服了常规大规模生产中的难题。 光波导使得可以实现各种光学器件和光电路之间的连接，并且将来成为光学印刷电路板（PCB）和封装系统（SOP）的源技术。

公开(公告)号：US20070054509A1

公开(公告)日：2007-03-08

申请号：US11515859

申请日：2006-09-06

Applicant: Nam-hoon Baek ,  A-in Cho

Inventor： Nam-hoon Baek ,  A-in Cho

IPC: H01R29/00

CPC classification number: H04N5/268

Abstract: An apparatus including a multifunctional input and output jack and a method using the same are provided, in which a control unit generates a control voltage according to predetermined settings, a signal-processing unit processes a progress path so that at least one of control and image signals with respect to a predetermined external device is input or output according to the control voltage, a switch unit processes a progress path so that a sound signal with respect to the external device is input or output according to the control voltage, and an input and output unit that inputs or outputs at least one of the control, image and sound signals according to the progress path.

Abstract translation: 提供一种包括多功能输入和输出插孔的装置及其使用方法，其中控制单元根据预定设置产生控制电压，信号处理单元处理进度路径，使得控制和图像中的至少一个 相对于预定的外部设备的信号根据控制电压被输入或输出，开关单元处理进行路径，使得根据控制电压输入或输出相对于外部设备的声音信号，以及输入和 输出单元，其根据进度路径输入或输出控制，图像和声音信号中的至少一个。

公开(公告)号：US20050120492A1

公开(公告)日：2005-06-09

申请号：US10486330

申请日：2003-05-15

Applicant: Bon Koo ,  Kwon Hong ,  Jae Lyu ,  Woon Lee ,  Jong Bang ,  Min Oh ,  Kweon Son ,  Jong Kim ,  In Cho

Inventor： Bon Koo ,  Kwon Hong ,  Jae Lyu ,  Woon Lee ,  Jong Bang ,  Min Oh ,  Kweon Son ,  Jong Kim ,  In Cho

IPC: D06F33/02 ,  D06F37/30 ,  D06F37/40 ,  D06F39/14 ,  H02P3/18 ,  H02P3/22 ,  H02P27/06

CPC classification number: D06F37/304 ,  D06F2202/065 ,  D06F2204/065 ,  H02P3/22 ,  Y02B40/52

Abstract: A method of controlling a motor-driven washing machine and a control system that controls a motor or any other components of the washing machine are disclosed. The method includes the steps of generating an interruption command for braking a motor in motion during a wash cycle, applying a phase-reversed voltage to a voltage input terminal of the motor in motion, and electrically shorting the input terminal of the motor for a predetermined period of time if a second phase-reversed voltage generated by the motor is higher than or equal to a critical voltage level. Using such method, a motor-clutch mechanism is prevented front generating a noise and from being damaged during a wash cycle.

Abstract translation: 一种控制电动机驱动的洗衣机以及控制马达或洗衣机的任何其它部件的控制系统的方法中公开。 该方法包括用于一个洗涤周期中的制动运动中的马达产生的中断指令，施加相位反转的电压，以在运动的电动机的电压输入端子，和电短路电动机的输入端，用于在预定的步骤 的时间段，如果由电动机产生一个第二相位反向电压高于或等于临界电压电平。 使用这种方法，一个电动机离合器机构防止前产生的噪音和从一个洗涤循环期间被损坏。

公开(公告)号：US06872270B2

公开(公告)日：2005-03-29

申请号：US09838535

申请日：2001-04-19

Applicant: Byoung In Cho ,  Jeffrey W. Manning ,  M. Brad Giddens ,  James W. Thomte

Inventor： Byoung In Cho ,  Jeffrey W. Manning ,  M. Brad Giddens ,  James W. Thomte

IPC: B32B3/12 ,  B32B5/18 ,  B32B31/14

CPC classification number: B32B3/12 ,  B32B5/18 ,  B32B5/245 ,  B32B27/10 ,  B32B27/12 ,  B32B27/32 ,  B32B27/40 ,  B32B29/007 ,  B32B2038/0076 ,  B32B2266/0278 ,  B32B2553/026 ,  Y10T428/31551

Abstract: There is disclosed a method of forming a foam product, comprising the steps of forming a layer of uncured polymeric foam; applying to the layer of uncured foam a layer of bubble pack, such that the bubbles that extend outwardly from the bubble pack at least partially penetrate into the uncured foam; and curing the layer of uncured polymeric foam. Products made by the process are also disclosed.

Abstract translation: 公开了一种形成泡沫产品的方法，包括以下步骤：形成未固化的聚合物泡沫层; 将未固化的泡沫层施加到一层气泡组件，使得从气泡组件向外延伸的气泡至少部分地渗透到未固化的泡沫体中; 并固化未固化的聚合物泡沫层。 还披露了由该方法制成的产品。

公开(公告)号：US06266286B1

公开(公告)日：2001-07-24

申请号：US09457909

申请日：1999-12-08

Applicant: Soo-In Cho ,  Jong-Hyun Choi

Inventor： Soo-In Cho ,  Jong-Hyun Choi

IPC: G11C700

CPC classification number: G11C29/025 ,  G11C11/401 ,  G11C29/006 ,  G11C29/02 ,  G11C29/50

Abstract: A wafer burn-in test circuit of a semiconductor memory device having a plurality of memory cells arranged in a row/column matrix, is provided, including:a sub word line driver connected to first and second word line groups each connected to true cells and complement cells forming the memory cells, and responding to a predecoded low address; and first and second power lines respectively supplying power to the corresponding first and second power line groups by a switching operation of the sub word line driver, wherein a ground power source is applied to the first and second power lines during a normal operation, and the ground power source and a step-up power source are alternately applied to the first and second power lines during a wafer burn-in test operation.

Abstract translation: 提供了具有以行/列矩阵排列的多个存储单元的半导体存储器件的晶片老化测试电路，包括：连接到每个连接到真实单元的第一和第二字线组的子字线驱动器，以及 形成存储器单元的补码单元，以及对预解码的低地址的响应; 以及分别通过子字线驱动器的切换操作向对应的第一和第二电力线组提供电力的第一和第二电力线，其中在正常操作期间将地电源施加到第一和第二电力线，并且 接地电源和升压电源在晶片老化测试操作期间交替施加到第一和第二电源线。

公开(公告)号：US6075384A

公开(公告)日：2000-06-13

申请号：US49739

申请日：1998-03-27

Applicant: Jae-Yoon Sim ,  Hong-Joon Park ,  Soo-In Cho ,  Jung-Bae Lee

Inventor： Jae-Yoon Sim ,  Hong-Joon Park ,  Soo-In Cho ,  Jung-Bae Lee

IPC: H03K17/00 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/018592

Abstract: A bidirectional input/output buffer operates in a current mode to increase the data transfer rate between devices connected by a bidirectional transmission line. The buffer includes an output current source for generating an output current responsive to a data output signal. The output current is combined with an output current indicative of a data input signal received from another device over a transmission line, thereby forming a mixed current signal. The data input signal is restored from the mixed signal by a restoring circuit that compares the mixed signal to a reference current that depends on the value of the data output signal. The restoring circuit includes a current mirror and a reference current source that generates a reference current in response to the data output signal. To provide additional performance, an embodiment of a bidirectional input/output buffer utilizes a switchless structure having two comparators that compare the mixed signal to two different reference signals, thereby generating two comparison signals. A selector circuit selects one of the two comparison signals as the restored data input signal responsive to the data output signal.

Abstract translation: 双向输入/输出缓冲器以当前模式工作，以增加通过双向传输线连接的设备之间的数据传输速率。 缓冲器包括用于响应于数据输出信号产生输出电流的输出电流源。 输出电流与表示通过传输线从另一设备接收的数据输入信号的输出电流组合，从而形成混合电流信号。 数据输入信号通过将混合信号与取决于数据输出信号的值的参考电流进行比较的恢复电路从混合信号中恢复。 恢复电路包括响应于数据输出信号产生参考电流的电流镜和参考电流源。 为了提供额外的性能，双向输入/输出缓冲器的实施例利用具有两个比较器的无开关结构，其将混合信号与两个不同的参考信号进行比较，从而产生两个比较信号。 选择器电路根据数据输出信号选择两个比较信号中的一个作为恢复的数据输入信号。

公开(公告)号：US5659519A

公开(公告)日：1997-08-19

申请号：US585597

申请日：1996-01-16

Applicant: Hyun-Seok Lee ,  Soo-In Cho

Inventor： Hyun-Seok Lee ,  Soo-In Cho

IPC: G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C5/145

Abstract: A semiconductor memory device including at least two boosting voltage circuits which independently boost a supply voltage power level to a boosted voltage power level. A plurality of memory cell arrays each input the supply voltage power and store information therein. Driving circuits are connected to each of the memory cell arrays and supply the boosted voltage power to the memory cell arrays, the number of driving circuits preferably corresponding to the number of the boosting voltage circuits.

Abstract translation: 一种半导体存储器件，包括至少两个升压电压电路，其独立地将电源电压功率电平升高到提升的电压功率电平。 多个存储单元阵列分别输入电源电压并存储信息。 驱动电路连接到每个存储单元阵列，并将提升的电压电力提供给存储单元阵列，驱动电路的数量优选地对应于升压电压电路的数量。

公开(公告)号：US5446697A

公开(公告)日：1995-08-29

申请号：US068547

申请日：1993-05-28

Applicant: Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

Inventor： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

IPC: G11C5/14 ,  H02M3/07 ,  G11C13/00

CPC classification number: H02M3/07 ,  G11C5/145

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Abstract translation: 半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作 根据检测信号可变。 因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。