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    PIXEL SENSOR HAVING DOPED ISOLATION STRUCTURE SIDEWALL
    31.
    发明申请
    PIXEL SENSOR HAVING DOPED ISOLATION STRUCTURE SIDEWALL 有权
    具有分离隔离结构的PIXEL传感器

    公开(公告)号：US20070087463A1

    公开(公告)日：2007-04-19

    申请号：US11563531

    申请日：2006-11-27

    Applicant: James Adkisson ,  Mark Jaffe ,  Robert Leidy

    Inventor： James Adkisson ,  Mark Jaffe ,  Robert Leidy

    IPC: H01L21/00

    CPC classification number: H01L27/14603 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14683

    Abstract: A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation structure is formed adjacent to the photosensitive device pinning layer. The trench isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffiusion process whereby dopant materials present in a doped material layer formed along selected portions in the trench are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a comer, or a comer portion thereof, which may block the angled implant material.

    Abstract translation: 形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。 在光敏器件钉扎层附近形成沟槽隔离结构。 沟槽隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。 用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散过程，由此在退火期间，存在于沿着沟槽中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。 可替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其拐角部分来减小其尺寸来执行。

    PINNING LAYER FOR PIXEL SENSOR CELL AND METHOD THEREOF
    32.
    发明申请
    PINNING LAYER FOR PIXEL SENSOR CELL AND METHOD THEREOF 审中-公开
    用于像素传感器单元的密封层及其方法

    公开(公告)号：US20070023796A1

    公开(公告)日：2007-02-01

    申请号：US11161224

    申请日：2005-07-27

    Applicant: James Adkisson ,  John Ellis-Monaghan

    Inventor： James Adkisson ,  John Ellis-Monaghan

    IPC: H01L31/113 ,  H01L31/062

    CPC classification number: H01L27/14689 ,  H01L27/14609 ,  H01L27/1463

    Abstract: A novel pixel sensor cell structure and method of manufacture. The pixel sensor cell includes a collection well region of a first conductivity type and a pinning layer formed in a substrate. The pinning layer includes a first impurity region of a second conductivity type and a second impurity region of the second conductivity type. The first and second impurity regions can be independently formed to affect multiple parameters of the pixel sensor cell.

    Abstract translation: 一种新颖的像素传感器单元结构及其制造方法。 像素传感器单元包括第一导电类型的收集阱区域和形成在衬底中的钉扎层。 钉扎层包括第二导电类型的第一杂质区和第二导电类型的第二杂质区。 可以独立地形成第一和第二杂质区域以影响像素传感器单元的多个参数。

    RECESSED GATE FOR AN IMAGE SENSOR
    33.
    发明申请
    RECESSED GATE FOR AN IMAGE SENSOR 有权
    图像传感器的门

    公开(公告)号：US20060124976A1

    公开(公告)日：2006-06-15

    申请号：US10905097

    申请日：2004-12-15

    Applicant: James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Jerome Lasky

    Inventor： James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Jerome Lasky

    IPC: H01L31/113 ,  H01L29/76 ,  H01L29/94

    CPC classification number: H01L27/14603 ,  H01L27/14601 ,  H01L27/14689 ,  H01L29/66621

    Abstract: A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.

    Abstract translation: 一种新颖的图像传感器单元结构及其制造方法。 成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层 在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区 。 栅极导体底部的一部分凹陷在基板的表面下方。 优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

    DEFECT DIAGNOSIS FOR SEMICONDUCTOR INTEGRATED CIRCUITS
    35.
    发明申请
    DEFECT DIAGNOSIS FOR SEMICONDUCTOR INTEGRATED CIRCUITS 失效
    半导体集成电路缺陷诊断

    公开(公告)号：US20060036975A1

    公开(公告)日：2006-02-16

    申请号：US10710879

    申请日：2004-08-10

    Applicant: James Adkisson ,  Greg Bazan ,  John Cohn ,  Francis Gravel ,  Leendert Huisman ,  Phillip Nigh ,  Leah Pastel ,  Kenneth Rowe ,  Thomas Sopchak ,  David Sweenor

    Inventor： James Adkisson ,  Greg Bazan ,  John Cohn ,  Francis Gravel ,  Leendert Huisman ,  Phillip Nigh ,  Leah Pastel ,  Kenneth Rowe ,  Thomas Sopchak ,  David Sweenor

    IPC: G06F17/50

    CPC classification number: G01R31/31718 ,  G01R31/318342

    Abstract: A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.

    Abstract translation: 一种半导体芯片缺陷诊断方法。 该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

    METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS
    38.
    发明申请
    METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS 有权
    将制造监控器添加到集成电路卡的方法

    公开(公告)号：US20070160920A1

    公开(公告)日：2007-07-12

    申请号：US11687731

    申请日：2007-03-19

    Applicant: James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

    Inventor： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

    IPC: G03F1/00 ,  G03C5/00 ,  G06F17/50

    CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

    Abstract translation: 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

    ON DEMAND CIRCUIT FUNCTION EXECUTION EMPLOYING OPTICAL SENSING
    39.
    发明申请
    ON DEMAND CIRCUIT FUNCTION EXECUTION EMPLOYING OPTICAL SENSING 失效
    使用光电传感器的需求电路功能执行

    公开(公告)号：US20070127172A1

    公开(公告)日：2007-06-07

    申请号：US11275058

    申请日：2005-12-06

    Applicant: Wagdi Abadeer ,  James Adkisson ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Michael Hauser ,  Jed Rankin ,  William Tonti

    Inventor： Wagdi Abadeer ,  James Adkisson ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Michael Hauser ,  Jed Rankin ,  William Tonti

    IPC: H02H9/00

    CPC classification number: H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad once the packaged chip is placed in system. No additional pins on the package are necessary.

    Abstract translation: 公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。 本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。 一旦封装的芯片放置在系统中，也可以将ESD保护装置从输入焊盘断开。 不需要额外的引脚。

    DAMASCENE COPPER WIRING OPTICAL IMAGE SENSOR
    40.
    发明申请
    DAMASCENE COPPER WIRING OPTICAL IMAGE SENSOR 有权
    DAMASCENE铜接线光学图像传感器

    公开(公告)号：US20070114622A1

    公开(公告)日：2007-05-24

    申请号：US11623977

    申请日：2007-01-17

    Applicant: James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Anthony Stamper

    Inventor： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Anthony Stamper

    IPC: H01L29/82

    CPC classification number: H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

    Abstract: A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a inner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

    Abstract translation: CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合具有改进的厚度均匀性的内部层间电介质叠层，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

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