公开(公告)号：US20110004794A1

公开(公告)日：2011-01-06

申请号：US12616529

申请日：2009-11-11

Applicant: Jeong-Hun Lee ,  Jeong-Tae Hwang

Inventor： Jeong-Hun Lee ,  Jeong-Tae Hwang

IPC: G11C29/10 ,  G06F11/263

CPC classification number: G11C29/46

Abstract: A semiconductor memory device is capable of performing a test operation in its various operation modes. Particularly, the semiconductor memory device can enter a test mode in other modes, as well as, an all bank pre-charge mode. The semiconductor memory device includes a test mode control block configured to generate a test signal enabled for a predetermined interval in an active mode, and a mode register set control block configured to enable a mode register set signal for a test operation in the predetermined interval in response to the test signal.

Abstract translation: 半导体存储器件能够在其各种操作模式下执行测试操作。 特别地，半导体存储器件可以进入其他模式的测试模式以及全部银行预充电模式。 半导体存储器件包括：测试模式控制块，被配置为在激活模式下产生预定间隔使能的测试信号;以及模式寄存器组控制模块，被配置为使得模式寄存器设置信号能够在预定间隔内进行测试操作 响应测试信号。

公开(公告)号：US20100290304A1

公开(公告)日：2010-11-18

申请号：US12494815

申请日：2009-06-30

Applicant: Jeong-Hun Lee ,  Yong-Mi Kim ,  Jeong-Tae Hwang

Inventor： Jeong-Hun Lee ,  Yong-Mi Kim ,  Jeong-Tae Hwang

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C7/02 ,  G11C7/22 ,  G11C7/222

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract translation: 半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线 响应于检测信号。

公开(公告)号：US20090070542A1

公开(公告)日：2009-03-12

申请号：US12034742

申请日：2008-02-21

Applicant: Jeong-hun LEE

Inventor： Jeong-hun LEE

IPC: G06F12/00

CPC classification number: G11B27/034 ,  G06F3/0604 ,  G06F3/0643 ,  G06F3/0679 ,  G11B27/32

Abstract: A method to divide a file or merge files using a file allocation table (FAT) in which the method to divide a file includes storing data of a first cluster, among data intended to be separated from the file, into a second cluster, and generating a first cluster chain and a second cluster chain using a file allocation table (FAT), the first cluster chain containing data remaining in the first cluster, and the second cluster containing data existing in the second cluster. As a result, time delay due to a file copy process and shortening of a lifespan of NAND flash are prevented, and a reserve capacity for editing purposes is minimized.

Abstract translation: 一种使用文件分配表（FAT）分割文件或合并文件的方法，其中分割文件的方法包括将要从文件分离的数据中的第一集群的数据存储到第二集群中，并且生成 使用文件分配表（FAT）的第一集群链和第二集群链，所述第一集群链包含剩余在所述第一集群中的数据，所述第二集群包含存在于所述第二集群中的数据。 结果，防止了由于文件复制处理引起的时间延迟和缩短NAND闪存的寿命，并且用于编辑目的的预留容量被最小化。

公开(公告)号：US09249728B2

公开(公告)日：2016-02-02

申请号：US13468218

申请日：2012-05-10

Applicant: Chan-Sun Lim ,  Myeong-Hyo Kim ,  Jong-Sub Shin ,  Young-Chang Shon ,  Jeong-Hun Lee

Inventor： Chan-Sun Lim ,  Myeong-Hyo Kim ,  Jong-Sub Shin ,  Young-Chang Shon ,  Jeong-Hun Lee

IPC: F02C7/08 ,  F02C6/16

CPC classification number: F02C7/08 ,  F02C6/16 ,  Y02E60/15

Abstract: A power generation system includes a compression unit which compresses a gas, a storage which stores the compressed gas output from the compression unit, a first expansion unit which generates first power and outputs a first exhaust gas, a heating unit which heats at least the stored gas output from the storage, a second expansion unit which generates second power and outputs a second exhaust gas, a first regenerator which performs a first heat exchange between the second exhaust gas and the stored gas output from the storage, to generate a first heat exchange gas used to generate the first power and a first regenerator gas, and a second regenerator which performs a second heat exchange between the first exhaust gas and the first regenerator gas to generate a second heat exchange gas used to generate the second power after heated at the heating unit.

Abstract translation: 发电系统包括压缩气体的压缩单元，存储从压缩单元输出的压缩气体的存储器，产生第一功率并输出第一排气的第一膨胀单元，至少加热存储的加热单元 从存储器输出的气体，产生第二功率并输出第二废气的第二膨胀单元，在第二排气和从储存器输出的储存气体之间进行第一热交换的第一再生器，以产生第一热交换 用于产生第一功率的气体和第一再生器气体;以及第二再生器，其在第一废气和第一再生器气体之间进行第二热交换，以产生用于在第二再生器加热后产生第二功率的第二热交换气体 加热单元

公开(公告)号：US08593886B2

公开(公告)日：2013-11-26

申请号：US13339050

申请日：2011-12-28

Applicant: Jeong Hun Lee

Inventor： Jeong Hun Lee

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C5/147 ,  G11C7/1045 ,  G11C7/1057 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2254

Abstract: A semiconductor system includes a controller configured to apply code signals for setting levels of a reference voltage and data, and to receive output data. The semiconductor system also includes a semiconductor device configured to receive the data for the respective levels of the reference voltage set according to the code signals, to compare the reference voltages with the data to generate new data, to store the new data as internal data, and to process the stored internal data to output as the output data.

Abstract translation: 半导体系统包括被配置为应用用于设置参考电压和数据的电平的代码信号并且接收输出数据的控制器。 半导体系统还包括：半导体器件，被配置为根据代码信号接收针对参考电压组的各个电平的数据，以将参考电压与数据进行比较以生成新数据，以将新数据存储为内部数据， 并处理存储的内部数据作为输出数据输出。

公开(公告)号：US20130114351A1

公开(公告)日：2013-05-09

申请号：US13404446

申请日：2012-02-24

Applicant: Jeong-Hun LEE

Inventor： Jeong-Hun LEE

IPC: G11C29/00 ,  G11C7/10

CPC classification number: G11C29/021 ,  G11C11/40 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/40 ,  G11C29/48

Abstract: A semiconductor device includes a data storage unit configured to receive input data, outputs the input data with a difference in voltage level between logic levels, and output comparison data whose logic level is distinguished from the input data; a test operation unit configured to determine a logic level of test data periodically in response to a data reference voltage whose voltage level is determined in response to a level test code during a test operation period defined by a test entry command and a test exit command, and generate a test result signal by comparing a logic level of the comparison data with the logic level of the test data; and a test operation sensing signal generation unit configured to generate a test operation sensing signal that is activated in response to the test entry command and inactivated in response to the test result signal.

Abstract translation: 半导体器件包括：数据存储单元，被配置为接收输入数据，输出具有逻辑电平之间的电压电平差的输入数据，以及逻辑电平与输入数据区分的输出比较数据; 测试操作单元，被配置为响应于在由测试输入命令和测试退出命令所定义的测试操作期间响应于电平测试代码确定其电压电平的数据参考电压周期性地确定测试数据的逻辑电平， 并通过将比较数据的逻辑电平与测试数据的逻辑电平进行比较来产生测试结果信号; 以及测试操作感测信号生成单元，被配置为生成响应于测试输入命令被激活并且响应于测试结果信号而被去激活的测试操作感测信号。

公开(公告)号：US20130107641A1

公开(公告)日：2013-05-02

申请号：US13339050

申请日：2011-12-28

Applicant: Jeong Hun LEE

Inventor： Jeong Hun LEE

IPC: G11C5/14 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C7/1045 ,  G11C7/1057 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2254

Abstract: A semiconductor system includes a controller configured to apply code signals for setting levels of a reference voltage and data, and to receive output data. The semiconductor system also includes a semiconductor device configured to receive the data for the respective levels of the reference voltage set according to the code signals, to compare the reference voltages with the data to generate new data, to store the new data as internal data, and to process the stored internal data to output as the output data.

Abstract translation: 半导体系统包括被配置为应用用于设置参考电压和数据的电平的代码信号并且接收输出数据的控制器。 半导体系统还包括：半导体器件，被配置为根据代码信号接收针对参考电压组的各个电平的数据，以将参考电压与数据进行比较以生成新数据，以将新数据存储为内部数据， 并处理存储的内部数据作为输出数据输出。

公开(公告)号：US20120008431A1

公开(公告)日：2012-01-12

申请号：US13033685

申请日：2011-02-24

Applicant: Jeong Hun LEE

Inventor： Jeong Hun LEE

IPC: G11C5/14 ,  G11C7/00 ,  H03K17/28 ,  H03K5/22 ,  H03K17/00

CPC classification number: G11C11/4072 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  H03K5/08 ,  H03M1/765

Abstract: An integrated circuit includes a reference voltage level setting circuit and a reference voltage generation circuit. The reference voltage level setting circuit is configured to set a level of an input reference voltage to a preset level in a power-up period or a self-refresh mode. The reference voltage generation circuit is configured to select one of a plurality of reference voltages and output the selected reference voltage as the input reference voltage when the power-up period is ended and an operation mode is not in the self-refresh mode.

Abstract translation: 集成电路包括参考电压电平设置电路和参考电压产生电路。 参考电压电平设置电路被配置为在上电周期或自刷新模式下将输入参考电压的电平设置为预设电平。 参考电压产生电路被配置为当上电周期结束并且操作模式不处于自刷新模式时，选择多个参考电压中的一个并输出所选择的参考电压作为输入参考电压。

公开(公告)号：USD651444S1

公开(公告)日：2012-01-03

申请号：US29381577

申请日：2010-12-21

Applicant: Jeong Hun Lee

Designer： Jeong Hun Lee

公开(公告)号：US20110235443A1

公开(公告)日：2011-09-29

申请号：US13155901

申请日：2011-06-08

Applicant: Jeong Hun Lee ,  Yong Mi Kim ,  Jeong Tae Hwang

Inventor： Jeong Hun Lee ,  Yong Mi Kim ,  Jeong Tae Hwang

IPC: G11C5/14 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C7/02 ,  G11C7/22 ,  G11C7/222

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract translation: 半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线 响应于检测信号。