公开(公告)号：US07362647B2

公开(公告)日：2008-04-22

申请号：US11529882

申请日：2006-09-30

Applicant: Jui-Jen Wu

Inventor： Jui-Jen Wu

IPC: G11C11/00

CPC classification number: G11C5/147 ,  G11C11/417

Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device and a second terminal coupled to the node of the integrated circuit module for controlling the switch device to pass the supply voltage to the node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module, the switch control module having at least one capacitor for selectively discharging the node, thereby creating the substantial voltage drop for the supply voltage across the switch device.

公开(公告)号：US07271644B2

公开(公告)日：2007-09-18

申请号：US11328780

申请日：2006-01-10

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Hung-Jen Liao

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Hung-Jen Liao

IPC: H01H37/76 ,  H01H85/00

CPC classification number: G11C11/56 ,  G11C17/18

Abstract: An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.

Abstract translation: 用于编程电熔丝的集成电路包括耦合到电熔丝的第一编程装置，用于选择性地为其提供第一编程电流;以及耦合到电熔丝的第二编程装置，用于选择性地将其提供给第二编程电流。 检测模块耦合到电熔丝，用于产生指示电熔丝的电阻电平的输出，其中电阻电平具有三个或更多个预定状态，这些状态通过用第一或第二编程电流选择性地编程电熔丝来提供。

公开(公告)号：US07019534B2

公开(公告)日：2006-03-28

申请号：US10810383

申请日：2004-03-26

Applicant: Jui-Jen Wu

Inventor： Jui-Jen Wu

IPC: H01H85/30 ,  G01R31/08

CPC classification number: G11C29/02 ,  G01R31/07 ,  G11C17/16 ,  G11C29/027

Abstract: A fuse detection circuit has; a fuse (102) under detection to produce a first voltage in the first arm in response to a read signal; a reference fuse (108) to produce a second voltage in response to the read signal; a sensing circuit (124) to sense the first voltage and the second voltage as status value data of the fuse under detection; a latch circuit (136) to keep the data in the sensing circuit; and a timing control circuit (138) to turn off the fuse bridge circuit independently of the read signal.

Abstract translation: 保险丝检测电路具有： 检测到的熔丝（102），以响应于读取信号在第一臂中产生第一电压; 参考熔丝（108），用于响应于读取信号产生第二电压; 感测电路（124），用于感测第一电压和第二电压作为被检测的熔丝的状态值数据; 锁存电路（136），用于将数据保持在感测电路中; 以及定时控制电路（138），以独立于读取信号来关断熔丝桥电路。

公开(公告)号：US08848419B2

公开(公告)日：2014-09-30

申请号：US13570305

申请日：2012-08-09

Applicant: Jui-Jen Wu ,  Meng-Fan Chang

Inventor： Jui-Jen Wu ,  Meng-Fan Chang

IPC: G11C11/00

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C7/14 ,  G11C11/419

Abstract: A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different resistances at logic states “0” and “1.” A reference bit line is coupled to the supply voltage through a comparison resistance value, especially a resistance between high and low resistance of the memory element in the two logic states. Voltages on the bit line and reference bit line ramp toward a switching threshold at rates related to the resistance values. The first line to discharge to switching threshold voltage sets the sense circuit latch.

Abstract translation: 数字存储元件具有用于读取存储在位单元中的值的读出电路锁存器。 在寻址字线之前，位线是预先充电的。 在读取操作期间，位线通过位逻辑状态“0”和“1”处具有不同电阻的位单元存储元件耦合到电源电压。参考位线通过比较电阻值耦合到电源电压 特别是在两个逻辑状态下存储元件的高电阻和低电阻之间的电阻。 在与电阻值相关的速率下，位线上的电压和参考位线斜坡转向切换阈值。 第一行放电到开关阈值电压设置感测电路锁存器。

公开(公告)号：US08351280B2

公开(公告)日：2013-01-08

申请号：US12908670

申请日：2010-10-20

Applicant: Jui-Jen Wu ,  Shao-Yu Chou

Inventor： Jui-Jen Wu ,  Shao-Yu Chou

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/14 ,  G11C11/412 ,  G11C11/413

Abstract: A circuit includes a reference data line configured to receive a reference voltage value, a memory cell, a data line coupled to the memory cell and configured to have a data logic value associated with data stored in the memory cell, a first circuit coupled to the reference data line and to the data line, and an output node configured to selectively receive the data logic value from the data line or receive the data logic value through the first circuit, based on the reference voltage value and a trip point used to trigger the first circuit to provide the data logic value through the first circuit.

Abstract translation: 电路包括被配置为接收参考电压值的参考数据线，存储器单元，耦合到存储器单元的数据线，并被配置为具有与存储在存储单元中的数据相关联的数据逻辑值，第一电路耦合到 参考数据线和数据线，以及输出节点，被配置为基于参考电压值和用于触发数据逻辑值的触发点，从数据线选择性地接收数据逻辑值或通过第一电路接收数据逻辑值 第一电路通过第一电路提供数据逻辑值。

公开(公告)号：US20120250440A1

公开(公告)日：2012-10-04

申请号：US13076039

申请日：2011-03-30

Applicant: Jui-Jen Wu

Inventor： Jui-Jen Wu

IPC: G11C7/12 ,  G11C7/06

CPC classification number: G11C7/065 ,  G11C7/1096 ,  G11C11/413

Abstract: A differential read write back sense amplifier circuit and corresponding methods. A memory array comprises a plurality of memory cells arranged in rows and columns; a plurality of read word lines coupled to the memory cells; a plurality of write word lines coupled to the memory cells arranged along rows of the memory array; a plurality of read bit line pairs coupled to the memory cells arranged in columns; a plurality of write bit line pairs coupled to the memory cells arranged in columns; and at least one differential read write back sense amplifier coupled to a read bit line pair and coupled to a write bit line pair corresponding to one of the columns of memory cells, configured to differentially sense small signal read data on the read bit line pair, and output the sensed data onto the write bit line pair. Corresponding methods are disclosed.

Abstract translation: 差分读回写放大器电路及相应的方法。 存储器阵列包括以行和列排列的多个存储单元; 耦合到所述存储器单元的多个读取字线; 耦合到沿着存储器阵列的行布置的存储器单元的多个写入字线; 耦合到布置成列的存储单元的多个读位线对; 耦合到布置成列的存储单元的多个写位线对; 以及至少一个差分读写回读出放大器，耦合到读位线对并耦合到对应于存储单元列之一的写位线对，其被配置为差分地读取读位线对上的小信号读数据， 并将感测到的数据输出到写位线对上。 公开了相应的方法。

公开(公告)号：US20120099382A1

公开(公告)日：2012-04-26

申请号：US12908670

申请日：2010-10-20

Applicant: Jui-Jen WU ,  Shao-Yu CHOU

Inventor： Jui-Jen WU ,  Shao-Yu CHOU

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/14 ,  G11C11/412 ,  G11C11/413

Abstract: A circuit includes a reference data line configured to receive a reference voltage value, a memory cell, a data line coupled to the memory cell and configured to have a data logic value associated with data stored in the memory cell, a first circuit coupled to the reference data line and to the data line, and an output node configured to selectively receive the data logic value from the data line or receive the data logic value through the first circuit, based on the reference voltage value and a trip point used to trigger the first circuit to provide the data logic value through the first circuit.

Abstract translation: 电路包括被配置为接收参考电压值的参考数据线，存储器单元，耦合到存储器单元的数据线，并被配置为具有与存储在存储单元中的数据相关联的数据逻辑值，第一电路耦合到 参考数据线和数据线，以及输出节点，被配置为基于参考电压值和用于触发数据逻辑值的触发点，从数据线选择性地接收数据逻辑值或通过第一电路接收数据逻辑值 第一电路通过第一电路提供数据逻辑值。

公开(公告)号：US20120051151A1

公开(公告)日：2012-03-01

申请号：US12872135

申请日：2010-08-31

Applicant: Jui-Jen WU ,  Shau-Wei LU ,  Robert LO ,  Kun-Hsi LI

Inventor： Jui-Jen WU ,  Shau-Wei LU ,  Robert LO ,  Kun-Hsi LI

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C7/1015 ,  G11C11/412 ,  G11C11/413

Abstract: A memory includes a memory cell, two word lines coupled to the memory cell, two bit lines coupled to the memory cell, and a write assist cell. The write assist cell is configured to transfer data of one bit line in a write operation to the other bit line in a read operation when one word line is used for the write operation, the other word line is used for the read operation, and the two word lines are asserted simultaneously.

Abstract translation: 存储器包括存储器单元，耦合到存储器单元的两个字线，耦合到存储器单元的两个位线以及写入辅助单元。 写入辅助单元被配置为当一个字线用于写入操作时，在读取操作中将写入操作中的一个位线的数据传送到另一个位线，另一个字线用于读取操作，并且 两个字线同时被断言。

公开(公告)号：US20100124099A1

公开(公告)日：2010-05-20

申请号：US12273959

申请日：2008-11-19

Applicant: Jui-Jen Wu ,  Yen-Huei Chen ,  Shao-Yu Chou ,  Hung-Jen Liao

Inventor： Jui-Jen Wu ,  Yen-Huei Chen ,  Shao-Yu Chou ,  Hung-Jen Liao

IPC: G11C11/412

CPC classification number: G11C11/412

Abstract: This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.

Abstract translation: 本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有存储节点的一对交叉耦合的反相器，以及具有栅极端子，连接到存储节点的第一和第二源极/漏极端子的NMOS晶体管， 分别读取字线（RWL）和读位线（RBL），RWL和RBL在读操作期间被激活，并且在任何写操作期间未被激活。

公开(公告)号：US07468903B2

公开(公告)日：2008-12-23

申请号：US11598385

申请日：2006-11-13

Applicant: Dao-Ping Wang ,  Hung-Jen Liao ,  Kun Lung Chen ,  Yung-Lung Lin ,  Jui-Jen Wu ,  Chen Yen-Huei

Inventor： Dao-Ping Wang ,  Hung-Jen Liao ,  Kun Lung Chen ,  Yung-Lung Lin ,  Jui-Jen Wu ,  Chen Yen-Huei

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C8/08 ,  G11C11/413 ,  G11C11/418

Abstract: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.