公开(公告)号：US08462540B2

公开(公告)日：2013-06-11

申请号：US13284532

申请日：2011-10-28

Applicant: Meng-Fan Chang ,  Lai-Fu Chen ,  Jui-Jen Wu ,  Hiroyuki Yamauchi

Inventor： Meng-Fan Chang ,  Lai-Fu Chen ,  Jui-Jen Wu ,  Hiroyuki Yamauchi

IPC: G11C11/412

CPC classification number: G11C11/412

Abstract: A static random access memory cell comprising a first inverter, a second inverter, a first transistor, a second transistor, and a third transistor. The first inverter is cross-coupled with the second inverter. The first transistor is connected with a write word line, a write bit line, and a first output node of the first inverter. The second transistor is connected with a complementary write bit line, the write word line, and a second output node of the second inverter. The third transistor is connected with a read bit line, a read word line, and the first input node of the first inverter to form a read port transistor, and a read port is formed. The read port transistor has a feature of asymmetric threshold voltage, and the read bit line swing can be expanded by the decrease of clamping current or the boosted read bit line.

Abstract translation: 一种静态随机存取存储单元，包括第一反相器，第二反相器，第一晶体管，第二晶体管和第三晶体管。 第一个反相器与第二个反相器交叉耦合。 第一晶体管与第一反相器的写字线，写位线和第一输出节点连接。 第二晶体管与第二反相器的互补写位线，写字线和第二输出节点连接。 第三晶体管与读位线，读字线和第一反相器的第一输入节点连接，形成读端口晶体管，形成读端口。 读端口晶体管具有不对称阈值电压的特征，并且可以通过钳位电流或升压读位线的减小来扩展读位线摆幅。

公开(公告)号：US20130107609A1

公开(公告)日：2013-05-02

申请号：US13284532

申请日：2011-10-28

Applicant: Meng-Fan Chang ,  Lai-Fu Chen ,  Jui-Jen Wu ,  Hiroyuki Yamauchi

Inventor： Meng-Fan Chang ,  Lai-Fu Chen ,  Jui-Jen Wu ,  Hiroyuki Yamauchi

IPC: G11C11/40

CPC classification number: G11C11/412

Abstract: A static random access memory cell comprising a first inverter, a second inverter, a first transistor, a second transistor, and a third transistor. The first inverter is cross-coupled with the second inverter. The first transistor is connected with a write word line, a write bit line, and a first output node of the first inverter. The second transistor is connected with a complementary write bit line, the write word line, and a second output node of the second inverter. The third transistor is connected with a read bit line, a read word line, and the first input node of the first inverter to form a read port transistor, and a read port is formed. The read port transistor has a feature of asymmetric threshold voltage, and the read bit line swing can be expanded by the decrease of clamping current or the boosted read bit line.

Abstract translation: 一种静态随机存取存储单元，包括第一反相器，第二反相器，第一晶体管，第二晶体管和第三晶体管。 第一个反相器与第二个反相器交叉耦合。 第一晶体管与第一反相器的写字线，写位线和第一输出节点连接。 第二晶体管与第二反相器的互补写位线，写字线和第二输出节点连接。 第三晶体管与读位线，读字线和第一反相器的第一输入节点连接，形成读端口晶体管，形成读端口。 读端口晶体管具有不对称阈值电压的特征，并且可以通过钳位电流或升压读位线的减小来扩展读位线摆幅。

公开(公告)号：US08848419B2

公开(公告)日：2014-09-30

申请号：US13570305

申请日：2012-08-09

Applicant: Jui-Jen Wu ,  Meng-Fan Chang

Inventor： Jui-Jen Wu ,  Meng-Fan Chang

IPC: G11C11/00

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C7/14 ,  G11C11/419

Abstract: A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different resistances at logic states “0” and “1.” A reference bit line is coupled to the supply voltage through a comparison resistance value, especially a resistance between high and low resistance of the memory element in the two logic states. Voltages on the bit line and reference bit line ramp toward a switching threshold at rates related to the resistance values. The first line to discharge to switching threshold voltage sets the sense circuit latch.

Abstract translation: 数字存储元件具有用于读取存储在位单元中的值的读出电路锁存器。 在寻址字线之前，位线是预先充电的。 在读取操作期间，位线通过位逻辑状态“0”和“1”处具有不同电阻的位单元存储元件耦合到电源电压。参考位线通过比较电阻值耦合到电源电压 特别是在两个逻辑状态下存储元件的高电阻和低电阻之间的电阻。 在与电阻值相关的速率下，位线上的电压和参考位线斜坡转向切换阈值。 第一行放电到开关阈值电压设置感测电路锁存器。

公开(公告)号：US08653877B2

公开(公告)日：2014-02-18

申请号：US13349982

申请日：2012-01-13

Applicant: Che-Wei Wu ,  Meng-Fan Chang

Inventor： Che-Wei Wu ,  Meng-Fan Chang

IPC: H03L5/00

CPC classification number: H03K3/35613 ,  H03K3/356182 ,  H03K19/0013

Abstract: A current mirror modified level shifter includes a pair of PMOS including a PMOS (MPL) and a PMOS (MPR), wherein a Vot node connected to a drain of the PMOS (MPR); a pair of NMOS including NMOS (MNL) and a NMOS (MNR), wherein sources of the PMOS (MPL) and the PMOS (MPR) are coupled to a high voltage (HV), respectively; gates of the PMOS (MPL) and the PMOS (MPR) coupled together through a Vm node which located between the gates of the PMOS (MPL) and the PMOS (MPR); and a suspended PMOS (MPM) coupled to drain of the PMOS (MPL), the Vm node being coupled to a Va node between drain of the suspend PMOS (MPM) and drain of the NMOS (MNL).

Abstract translation: 电流镜修改电平移位器包括一对包括PMOS（MPL）和PMOS（MPR）的PMOS，其中连接到PMOS（MPR）的漏极的Vot节点; 包括NMOS（MNL）和NMOS（MNR）的一对NMOS，其中PMOS（MPL）和PMOS（MPR）的源极分别耦合到高电压（HV）; 通过位于PMOS（MPL）和PMOS（MPR）的栅极之间的Vm节点耦合在一起的PMOS（MPL）和PMOS（MPR）的栅极; 以及耦合到PMOS（MPL）的漏极的悬浮PMOS（MPM），Vm节点耦合到暂停PMOS（MPM）的漏极和NMOS（MNL）的漏极之间的Va节点。

公开(公告)号：US20110270555A1

公开(公告)日：2011-11-03

申请号：US12851547

申请日：2010-08-05

Applicant: Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

Inventor： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC: G06F19/00 ,  G01R19/00

CPC classification number: G01R31/2837 ,  G11C13/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  H01L22/34

Abstract: A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result.

Abstract translation: 提供了一种过程变化检测装置和工艺变化检测方法。 过程变化检测装置包括处理变化检测器和补偿信号发生器。 过程变化检测器包括第一过程变化检测部件，第二过程变化检测部件和电流比较器。 第一处理变化检测部件的通道是第一导电型，第二处理变化检测部件的通道是第二导电型，其中上述第一导电类型与第二导电类型不同。 电流比较器连接到第一处理变化检测部件和第二处理变化检测部件，用于比较两个部件之间的电流差异并输出当前的比较结果。 补偿信号发生器连接到过程变化检测器，并根据当前比较结果产生相应的补偿信号。

公开(公告)号：US08392132B2

公开(公告)日：2013-03-05

申请号：US12851547

申请日：2010-08-05

Applicant: Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

Inventor： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC: G06F19/00

CPC classification number: G01R31/2837 ,  G11C13/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  H01L22/34

Abstract: A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result.

Abstract translation: 提供了一种过程变化检测装置和工艺变化检测方法。 过程变化检测装置包括处理变化检测器和补偿信号发生器。 过程变化检测器包括第一过程变化检测部件，第二过程变化检测部件和电流比较器。 第一处理变化检测部件的通道是第一导电型，第二处理变化检测部件的通道是第二导电型，其中上述第一导电类型与第二导电类型不同。 电流比较器连接到第一处理变化检测部件和第二处理变化检测部件，用于比较两个部件之间的电流差异并输出当前的比较结果。 补偿信号发生器连接到过程变化检测器，并根据当前比较结果产生相应的补偿信号。

公开(公告)号：US08320211B1

公开(公告)日：2012-11-27

申请号：US13108550

申请日：2011-05-16

Applicant: Meng-Fan Chang ,  Yu-Fan Lin ,  Shin-Jang Shen ,  Yu-Der Chih

Inventor： Meng-Fan Chang ,  Yu-Fan Lin ,  Shin-Jang Shen ,  Yu-Der Chih

IPC: G11C7/06 ,  H03F3/16

CPC classification number: G11C16/06 ,  G11C7/06 ,  G11C16/26

Abstract: A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.

Abstract translation: 公开了一种具有低偏移调整的电流检测放大器及其低失调调整方法。 电流检测放大器包括感测单元，均衡单元和偏置补偿单元。 感测单元包括读出放大器，锁存电路，第一预充电位线和第二预充电位线。 均衡单元电连接到第一和第二预充电位线，用于将第一预充电位线的电压和第二预充电位线的电压调节到相同的电位。 偏置补偿单元电连接到读出放大器，用于补偿电流检测放大器的输入偏移电压。

公开(公告)号：US20120293260A1

公开(公告)日：2012-11-22

申请号：US13108577

申请日：2011-05-16

Applicant: Meng-Fan Chang ,  Yu-Fan Lin ,  Shin-Jang Shen ,  Yu-Der Chih

Inventor： Meng-Fan Chang ,  Yu-Fan Lin ,  Shin-Jang Shen ,  Yu-Der Chih

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F1/0244 ,  H03F2200/261 ,  H03F2200/511 ,  H03F2203/45481 ,  H03F2203/45506

Abstract: A low-offset current-sense amplifier and an operating method thereof are disclosed. The low-offset current-sense amplifier includes a sense amplifier, a first current supply unit, a second current supply unit, and a processing unit. The first current supply unit is coupled to the sense amplifier, and includes a first transistor group and a first current output terminal. The second current supply unit is coupled to the sense amplifier, and includes a second transistor group and a second current output terminal. The processing unit controls the on/off of some transistors of the first transistor group and the second transistor group according to electric currents output from the first current output terminal and the second current output terminal, respectively.

Abstract translation: 公开了低失调电流检测放大器及其操作方法。 低失调电流检测放大器包括读出放大器，第一电流供应单元，第二电流供应单元和处理单元。 第一电流供应单元耦合到读出放大器，并且包括第一晶体管组和第一电流输出端子。 第二电流供应单元耦合到读出放大器，并且包括第二晶体管组和第二电流输出端。 处理单元分别根据从第一电流输出端子和第二电流输出端子输出的电流来控制第一晶体管组和第二晶体管组的一些晶体管的开/关。

公开(公告)号：US08274322B2

公开(公告)日：2012-09-25

申请号：US12906313

申请日：2010-10-18

Applicant: Meng-Fan Chang ,  Shin-Jang Shen ,  Wan-Ying Lu

Inventor： Meng-Fan Chang ,  Shin-Jang Shen ,  Wan-Ying Lu

IPC: G05F1/10

CPC classification number: H02M3/07

Abstract: The present invention discloses a charge pump system with low noise and high output current and voltage, comprising: a four phase clock generator used to generate a first signals group; a serial of delay circuits coupled to said four phase clock generator, wherein each of said delay circuits is coupled to a previous delay circuit relative to each of said delay circuits for delaying a signals group received from said previous delay circuit; a first charge pump circuit coupled to the four phase clock generator and the delay circuits; and an output terminal coupled to the first charge pump circuit; wherein high level of said first signal overlaps two sections of high level of said third signal to generate a first overlapping time and a second overlapping time, and said first overlapping time is not equal to said second overlapping time.

公开(公告)号：US07969193B1

公开(公告)日：2011-06-28

申请号：US12830469

申请日：2010-07-06

Applicant: Wei-Cheng Wu ,  Yen-Huei Chen ,  Meng-Fan Chang

Inventor： Wei-Cheng Wu ,  Yen-Huei Chen ,  Meng-Fan Chang

IPC: H03K19/0175

CPC classification number: H03K19/0175 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This disclosure uses a differential sensing and TSV timing control scheme for 3D-IC, which includes a first chip layer of the stacked device having a detecting circuits and a relative high ability driver horizontally coupled to the detecting circuits. A sensing circuit is coupled to the detecting circuits by a horizontal line, a first differential signal driver is coupled to the sensing circuit, horizontally. The Nth chip layer of the stacked device includes a Nth relative high ability driver and a Nth differential signal driver formed on the Nth chip layer. The Nth relative high ability driver is vertically coupled to the first relative high ability driver through one relative low loading TSV and (N−2) TSVs to act as dummy loadings. The TSV and (N−2) TSVs penetrate the stacked device from Nth chip layer to first chip layer. The TSV shares same configuration with the (N−2) TSVs. The Nth differential signal driver is vertically coupled to the first differential signal driver through a pair of TSVs and (N−2) pairs of TSVs, vertically. The pair of TSVs and the (N−2) TSVs penetrate the stacked device from the Nth chip layer to the first chip layer. Each of TSV is formed between a first and a second chip layers. Each of TSV is formed between any adjacent two chip layers of the stacked device.

Abstract translation: 本公开使用用于3D-IC的差分感测和TSV定时控制方案，其包括具有检测电路的堆叠装置的第一芯片层和水平耦合到检测电路的相对高能力驱动器。 感测电路通过水平线耦合到检测电路，第一差分信号驱动器水平地耦合到感测电路。 层叠器件的第N芯片层包括形成在第N芯片层上的第N相对高能力驱动器和第N差分信号驱动器。 第N相对高能力驱动器通过一个相对低负载TSV和（N-2）TSV垂直耦合到第一相对高能力的驱动器作为虚拟负载。 TSV和（N-2）TSV穿透层叠器件从第N个芯片层到第一个芯片层。 TSV与（N-2）TSV共享相同的配置。 第N个差分信号驱动器通过一对TSV和（N-2）对TSV垂直耦合到第一差分信号驱动器。 一对TSV和（N-2）TSV从第N个芯片层穿透层叠器件到第一芯片层。 每个TSV形成在第一和第二芯片层之间。 每个TSV形成在堆叠设备的任何相邻的两个芯片层之间。