公开(公告)号：US20110109636A1

公开(公告)日：2011-05-12

申请号：US12617638

申请日：2009-11-12

申请人： Shany-I CHAN ,  Ching-Yee Feng ,  Shih-Da Wu ,  Li-Kai Cheng ,  Li-Ling Chou ,  Yu-Kuo Chiang ,  Yu-Li (David) Ho

发明人： Shany-I CHAN ,  Ching-Yee Feng ,  Shih-Da Wu ,  Li-Kai Cheng ,  Li-Ling Chou ,  Yu-Kuo Chiang ,  Yu-Li (David) Ho

IPC分类号： G06F15/80 ,  G06F13/14 ,  G06F12/02

CPC分类号： G06F13/102 ,  G06F3/14 ,  G06F9/544 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/08 ,  G09G2360/126

摘要： The present invention sets forth a method and system for communicating with an external device through a processing unit in a graphics system of a computing device. In one embodiment, the method comprises allocating a first set of memory buffers having a first memory buffer and a second memory buffer in the graphics system based on an identification information of the external device, and invoking a first thread processor of the processing unit of the graphics system to perform services associated with a physical layer according to the identification information of the external device by storing a first data stream received from the external device through an I/O interface of the processing unit of the graphics system in the first memory buffer and retrieving a second data stream from the second memory buffer for transmission to the external device through the I/O interface.

摘要翻译： 本发明提出了一种通过计算设备的图形系统中的处理单元与外部设备进行通信的方法和系统。 在一个实施例中，该方法包括基于外部设备的识别信息，在图形系统中分配具有第一存储器缓冲器和第二存储器缓冲器的第一组存储器缓冲器，并且调用处理单元的第一线程处理器 图形系统，通过存储从外部设备接收的第一数据流，通过第一存储器缓冲器中的图形系统的处理单元的I / O接口，根据外部设备的识别信息来执行与物理层相关联的服务，以及 从第二存储器缓冲器检索第二数据流，以通过I / O接口传输到外部设备。

公开(公告)号：US20110108850A1

公开(公告)日：2011-05-12

申请号：US12914930

申请日：2010-10-28

申请人： Kai CHENG ,  Stefan Degroote

发明人： Kai CHENG ,  Stefan Degroote

IPC分类号： H01L27/085 ,  H01L21/8232

CPC分类号： H01L27/0605 ,  H01L21/8252 ,  H01L21/8258

摘要： An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.

摘要翻译： 公开了一种集成半导体衬底结构。 一方面，该结构包括衬底，GaN异质结构和半导体衬底层。 GaN异质结构存在于用于GaN基器件的定义的第一器件区域中，并且至少部分地被保护层覆盖。 半导体衬底层存在于用于CMOS器件定义的第二器件区域中。 至少GaN基异质结构和半导体衬底层中的至少一个设置在衬底中的至少一个沟槽中，使得GaN异质结构和半导体衬底层横向并置。

公开(公告)号：US20110101370A1

公开(公告)日：2011-05-05

申请号：US12916346

申请日：2010-10-29

申请人： Kai Cheng ,  Stefan Degroote

发明人： Kai Cheng ,  Stefan Degroote

IPC分类号： H01L29/66 ,  H01L21/20

CPC分类号： H01L21/02389 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66477 ,  H01L29/7786

摘要： A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions.

摘要翻译： 公开了一种半导体器件及其制造方法。 一方面，该器件在半导体衬底的顶部上包​​括半导体衬底和GaN型层叠层。 GaN型层堆叠具有至少一个缓冲层，第一有源层和第二有源层。 有源器件区可以在第一和第二有源层的界面处被定义。 半导体衬底存在于绝缘层上，并被图案化以根据预定图案限定沟槽，其包括位于有源器件区域下方的至少一个沟槽。 沟槽从绝缘层延伸到GaN型层堆叠的至少一个缓冲层中，并且在至少一个缓冲层内长满，从而获得第一和第二活性层至少在活性物质内连续 设备区域。

公开(公告)号：US07930464B2

公开(公告)日：2011-04-19

申请号：US12549491

申请日：2009-08-28

申请人： Linda J. Rankin ,  Paul R. Pierce ,  Gregory E. Dermer ,  Wen-Hann Wang ,  Kai Cheng ,  Richard H. Hofsheier ,  Nitin Y. Borkar

发明人： Linda J. Rankin ,  Paul R. Pierce ,  Gregory E. Dermer ,  Wen-Hann Wang ,  Kai Cheng ,  Richard H. Hofsheier ,  Nitin Y. Borkar

IPC分类号： G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

摘要翻译： 多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。 在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。 互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。 使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。 标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。 此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。 处理器内存总线，时钟和复位逻辑都保持不变。

公开(公告)号：US20110018819A1

公开(公告)日：2011-01-27

申请号：US12686393

申请日：2010-01-13

申请人： Yi-Te Yeh ,  Wei-Kai Cheng

发明人： Yi-Te Yeh ,  Wei-Kai Cheng

IPC分类号： G06F3/041

CPC分类号： G06F3/0416

摘要： For solving the defect that a hardware clock of a serial peripheral interface bus has to cooperate with slower software-simulated clocks used by a microprocessor while applying serial peripheral interface buses on a large-scale touch panel, a programmable logic device is used as a bridge of communicating information between the micro processor and sensors. Therefore, the microprocessor no longer has to take execution time to simulate serial peripheral interface buses by software, and is able to program hardware clocks of each of the serial peripheral interface buses according to speed requirements of different sensors, so that sensing signals of a plurality of sensors may be integrated on a touch device having the large-scale touch panel, and a processing speed of the touch device in processing the sensing signals may be optimized as a result.

摘要翻译： 为了解决串行外设接口总线的硬件时钟与微处理器使用的较慢软件仿真时钟配合的缺陷，同时在大型触摸面板上应用串行外设接口总线，可编程逻辑器件用作桥接器 在微处理器和传感器之间传送信息。 因此，微处理器不再需要花费时间通过软件模拟串行外设接口总线，并且可以根据不同传感器的速度要求对每个串行外设接口总线的硬件时钟进行编程，从而使多个传感器的感测信号 的传感器可以集成在具有大型触摸面板的触摸装置上，并且可以优化触摸装置处理感测信号的处理速度。

公开(公告)号：US20100270917A1

公开(公告)日：2010-10-28

申请号：US12699041

申请日：2010-02-03

申请人： Kai-Cheng CHUANG ,  Tzu-Ming WANG

发明人： Kai-Cheng CHUANG ,  Tzu-Ming WANG

IPC分类号： H01J63/04

CPC分类号： G02F1/133305 ,  G02F1/13439 ,  G02F1/167

摘要： A flexible electrode array substrate includes a flexible base and a plurality of pixel electrodes. The pixel electrodes are disposed on the flexible base and arranged in an array. The size of one of the pixel electrodes is different from that of another of the pixel electrodes. In addition, another flexible electrode array substrate including a flexible base and a plurality of bar electrodes is also provided. The bar electrodes are disposed on the flexible base and arranged in an array. The size of one of the bar electrodes is different from that of another of the bar electrodes. Besides, a flexible display device having one of the said flexible electrode array substrates is also provided.

摘要翻译： 柔性电极阵列基板包括柔性基座和多个像素电极。 像素电极设置在柔性基底上并排列成阵列。 像素电极之一的尺寸与另一个像素电极的尺寸不同。 此外，还提供了包括柔性基底和多个条形电极的另一柔性电极阵列基板。 棒状电极设置在柔性基底上并排列成阵列。 棒状电极中的一个的尺寸与另一个棒状电极的尺寸不同。 此外，还提供了具有所述柔性电极阵列基板之一的柔性显示装置。

公开(公告)号：US20100254137A1

公开(公告)日：2010-10-07

申请号：US12817144

申请日：2010-06-16

申请人： YI-KAI CHENG ,  JYH-LONG CHERN ,  PING-YU CHEN

发明人： YI-KAI CHENG ,  JYH-LONG CHERN ,  PING-YU CHEN

IPC分类号： F21V1/00

CPC分类号： G02B19/0009 ,  F21V5/04 ,  F21W2131/103 ,  F21Y2105/10 ,  F21Y2115/10 ,  G02B3/005 ,  G02B3/0056 ,  G02B3/0068 ,  G02B19/0014 ,  G02B19/0061 ,  G02B27/0961

摘要： An illuminating device includes a light source module for emitting light and an optical lens for adjusting the light. The light source module includes a reflecting unit and LEDs. The reflecting unit includes strip-shaped grooves each extending along a first direction. The LEDs are mounted on the reflecting unit in the grooves. The optical lens includes an array of lens units each including a main body, a light diverging portion and a light converging portion. The light diverging portion is for expanding a light field of the LEDs along the first direction. The light converging portion is for compressing the light field along a second direction. The reflecting unit is for further compressing the light field along the second direction.

摘要翻译： 照明装置包括用于发光的光源模块和用于调节光的光学透镜。 光源模块包括反射单元和LED。 反射单元包括沿着第一方向延伸的条形槽。 LED安装在凹槽中的反射单元上。 光学透镜包括各自包括主体，光发散部分和光会聚部分的透镜单元阵列。 光发散部分用于沿着第一方向扩展LED的光场。 光会聚部分用于沿着第二方向压缩光场。 反射单元用于沿着第二方向进一步压缩光场。

公开(公告)号：US20100254136A1

公开(公告)日：2010-10-07

申请号：US12817143

申请日：2010-06-16

申请人： YI-KAI CHENG ,  JYH-LONG CHERN ,  PING-YU CHEN

发明人： YI-KAI CHENG ,  JYH-LONG CHERN ,  PING-YU CHEN

IPC分类号： F21V5/00

CPC分类号： G02B19/0009 ,  F21V5/04 ,  F21W2131/103 ,  F21Y2105/10 ,  F21Y2115/10 ,  G02B3/005 ,  G02B3/0056 ,  G02B3/0068 ,  G02B19/0014 ,  G02B19/0061 ,  G02B27/0961

摘要： An illuminating device includes a light source module for emitting light and an optical lens configured for adjusting the light emitted from the light source module. The optical lens includes an array of lens units. Each lens unit includes a main body, a light diverging portion and a light converging portion. The main body includes a light incident surface and a light emitting surface opposite to the light incident surface. The light diverging portion is configured for expanding a light field along a first direction, and the light converging portion is configured for compressing a light field along a second direction. The light diverging portion and the light converging portion are formed on at least one of the light incident surface and the light emitting surface. The light diverging portion includes parallel protrusions distributed along the first direction.

摘要翻译： 照明装置包括用于发光的光源模块和被配置为调节从光源模块发射的光的光学透镜。 光学透镜包括透镜单元阵列。 每个透镜单元包括主体，发光部分和聚光部分。 主体包括光入射面和与光入射面相反的发光面。 光发散部被配置为沿着第一方向扩展光场，并且聚光部构造成沿着第二方向压缩光场。 光发散部分和聚光部分形成在光入射表面和发光表面中的至少一个上。 光发散部分包括沿着第一方向分布的平行突起。

公开(公告)号：US07734980B2

公开(公告)日：2010-06-08

申请号：US11165693

申请日：2005-06-24

申请人： James W. Alexander ,  Suresh Chittor ,  Dennis W. Brzezinski ,  Kai Cheng ,  Rajat Agarwal

发明人： James W. Alexander ,  Suresh Chittor ,  Dennis W. Brzezinski ,  Kai Cheng ,  Rajat Agarwal

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G06F11/1004 ,  H03M13/09 ,  H03M13/19

摘要： Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.

摘要翻译： 本发明的实施例一般涉及用于减轻完全缓冲存储器模块架构中的无声数据损坏的系统，装置和方法。 在一个实施例中，存储器控制器包括具有M位CRC和N位CRC的存储器通道位通道误差检测器，其中N小于M.如果至少一个位线 内存通道失败。 在一个实施例中，如果至少一个位通道已经失败，则存储器控制器选择性地将纠错码（ECC）的强错误检测能力与N位CRC结合起来，以指示重新发送故障数据的需要。 描述和要求保护其他实施例。

公开(公告)号：US20100039812A1

公开(公告)日：2010-02-18

申请号：US12491238

申请日：2009-06-25

申请人： YI-KAI CHENG ,  JYH-LONG CHERN ,  CHIH-MING LAI

发明人： YI-KAI CHENG ,  JYH-LONG CHERN ,  CHIH-MING LAI

IPC分类号： F21V1/00

CPC分类号： F21V13/04 ,  F21V5/002 ,  F21V5/04 ,  F21V13/12 ,  F21W2131/103 ,  F21Y2105/10 ,  F21Y2115/10 ,  G02B19/0028 ,  G02B19/0066

摘要： An exemplary illuminating device comprises a light source module, a light reflective module, a lens array and a light transmissive module. The lens array is for expanding a light field of the illuminating device along a first direction and compressing the light field of the illuminating device along a second direction. The light transmissive module comprises a first surface facing towards the lens array and a second surface opposite to the first surface. The second surface has a plurality of microstructures formed thereon thereby expanding the light field of the illuminating device along the first direction.

摘要翻译： 示例性照明装置包括光源模块，光反射模块，透镜阵列和透光模块。 透镜阵列用于沿着第一方向扩展照明装置的光场并沿第二方向压缩照明装置的光场。 透光模块包括面向透镜阵列的第一表面和与第一表面相对的第二表面。 第二表面上形成有多个微结构，从而使照明装置的光场沿着第一方向膨胀。