公开(公告)号：US20120038410A1

公开(公告)日：2012-02-16

申请号：US12856824

申请日：2010-08-16

申请人： Wei-Li LIAO ,  Sung-Chieh LIN ,  Kuoyuan HSU

发明人： Wei-Li LIAO ,  Sung-Chieh LIN ,  Kuoyuan HSU

IPC分类号： H03K17/687

CPC分类号： G11C29/026 ,  G11C29/028

摘要： An integrated circuit includes a sensing circuit, a fuse box, and a fuse bus decoder. The sensing circuit includes an output node, and the fuse box includes a plurality of switches coupled in series with a plurality of resistive elements. The fuse box is coupled to the output node of the sensing circuit from which the fuse box is configured to receive a current. The fuse bus decoder is coupled to the fuse box and includes at least one demultiplexer configured to receive a signal and in response output a plurality of control signals for selectively opening and closing the switches of the fuse box to adjust a resistance across the fuse box. A voltage of the output node of the sense amplifier is based on a resistance the fuse box and the current.

摘要翻译： 集成电路包括感测电路，保险丝盒和熔丝总线解码器。 感测电路包括输出节点，并且保险丝盒包括与多个电阻元件串联耦合的多个开关。 保险丝盒耦合到感测电路的输出节点，保险丝盒从该感应电路的输出节点配置为接收电流。 熔丝总线解码器耦合到保险丝盒，并且包括至少一个多路分解器，其被配置为接收信号，并且响应于输出多个控制信号，用于选择性地打开和闭合保险丝盒的开关以调整保险丝盒两端的电阻。 读出放大器的输出节点的电压基于保险丝盒和电流的电阻。

公开(公告)号：US20100329055A1

公开(公告)日：2010-12-30

申请号：US12824652

申请日：2010-06-28

申请人： Kuoyuan HSU ,  Po-Hung CHEN ,  Jiann-Tseng HUANG ,  Subramani KENGERI

发明人： Kuoyuan HSU ,  Po-Hung CHEN ,  Jiann-Tseng HUANG ,  Subramani KENGERI

IPC分类号： G11C29/00 ,  G11C17/16

CPC分类号： G11C13/00 ,  G11C5/147 ,  G11C7/00 ,  G11C7/062 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/004 ,  G11C16/26 ,  G11C17/16 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0045

摘要： A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.

摘要翻译： 一种具有第一电路的电路，其被配置为接收输入电压并产生产生流过电阻器件的第一电流的第一电压和产生第二电流的第二电压; 电耦合到所述电阻装置并具有产生第三电流的第三电压的节点; 以及第二电路，被配置为产生具有指示电阻装置的逻辑状态的逻辑状态的第四电压。

公开(公告)号：US20100328982A1

公开(公告)日：2010-12-30

申请号：US12788924

申请日：2010-05-27

申请人： Young Seog KIM ,  Kuoyuan HSU ,  Jacklyn CHANG

发明人： Young Seog KIM ,  Kuoyuan HSU ,  Jacklyn CHANG

IPC分类号： G11C15/00 ,  G06F17/50 ,  G11C7/10

CPC分类号： G06F17/5072 ,  G11C15/04 ,  H03K19/20

摘要： A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries.

摘要翻译： 静态CAM包括多个条目E，每个条目E包括多个CAM单元B和概要S.每个CAM单元B与存储单元M和比较器C相关联。通常，CAM接收到i个查找数据 线条。 当接收到数据时，存储器单元M提供CAM单元B中对应的比较器C的比较数据，以将比较的数据与接收到的数据进行比较。 如果所有比较的数据匹配所有接收到的数据行的条目，则该条目的命中。 但是，如果任何比较的数据与相应的数据行不匹配，那么该行有一个缺失，因此该条目的缺失。 根据应用程序，如果有一个或多个条目的命中，CAM将返回一个地址。