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    PROVIDING TIMING-CLOSED FINFET DESIGNS FROM PLANAR DESIGNS
    3.
    发明申请
    PROVIDING TIMING-CLOSED FINFET DESIGNS FROM PLANAR DESIGNS 有权
    从平面设计提供定时关闭FINFET设计

    公开(公告)号：US20130275935A1

    公开(公告)日：2013-10-17

    申请号：US13446418

    申请日：2012-04-13

    Applicant: Mahbub Rashed ,  David Doman ,  Dinesh Somasekhar ,  Yan Wang ,  Yunfei Deng ,  Navneet Jain ,  Jongwook Kye ,  Ali Keshavarzi ,  Subramani Kengeri ,  Suresh Venkatesan

    Inventor： Mahbub Rashed ,  David Doman ,  Dinesh Somasekhar ,  Yan Wang ,  Yunfei Deng ,  Navneet Jain ,  Jongwook Kye ,  Ali Keshavarzi ,  Subramani Kengeri ,  Suresh Venkatesan

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

    Abstract: An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.

    Abstract translation: 公开了一种从平面设计提供定时关闭的FinFET设计的方法。 实施例包括：接收与平面设计相关联的一个或多个平面单元; 基于平面单元和FinFET模型产生对应于平面设计的初始FinFET设计; 并处理初始FinFET设计以提供定时关闭的FinFET设计。 其他实施例包括：基于初始FinFET设计的时序分析确定与初始FinFET设计的路径相关联的竞争条件; 以及与解决与竞争条件相关联的持续违规的路径相关联的增加的延迟，其中初始FinFET设计的处理基于延迟增加。

    Charge shared match line differential generation for CAM
    5.
    发明授权
    Charge shared match line differential generation for CAM 有权
    为CAM共享匹配线差分生成

    公开(公告)号：US06343029B1

    公开(公告)日：2002-01-29

    申请号：US09782576

    申请日：2001-02-13

    Applicant: Subramani Kengeri ,  Steve Lim

    Inventor： Subramani Kengeri ,  Steve Lim

    IPC: G11C1500

    CPC classification number: G11C15/00 ,  G11C15/04

    Abstract: A content addressable memory (CAM) with built-in power saving management. The CAM includes a comparator circuit region that is coupled to a match line (ML) as well as a swing line (SL). The comparator circuit region is coupled to CAM cells. The comparator region is adapted for comparing match data with stored data within the CAM cells. The ML has its ML voltage level pre-charged to a pre-charge voltage level (Vc). Additionally, the SL is pre-charged to ground. In turn, in response to a data mismatch detected by the comparator, the ML voltage level drops from Vc by a ML voltage swing (Vswing) while the SL charge shares with the Ml. Advantageously, in response to this data mismatch, the SL charge shares with the ML such that Vswing is approximately less or equal to Vc/2. That is, the charge sharing prevents the ML from discharging all the way to ground. Thus, because Vswing is as large as Vc in a conventional CAM whereas Vswing is as large as about Vc/2 in the invention, the invention's Vswing restriction provides significant more power saving.

    Abstract translation: 内容可寻址存储器（CAM），内置省电管理。 CAM包括耦合到匹配线（ML）以及摆动线（SL）的比较器电路区域。 比较器电路区域耦合到CAM单元。 比较器区域适于将匹配数据与CAM单元内的存储数据进行比较。 ML具有预充电到预充电电压电平（Vc）的ML电压电平。 此外，SL预充电到地面。 反过来，响应于比较器检测到的数据不匹配，ML电压电平从Vc下降到ML电压摆幅（Vswing），而SL电荷与M1分配。 有利地，响应于该数据不匹配，SL电荷与ML共享，使得Vswing大致小于或等于Vc / 2。 也就是说，电荷共享防止了ML一路向地面放电。 因此，由于在本发明中Vswing与Vc一样大，而Vswing与Vc / 2一样大，所以本发明的Vswing限制提供了更大的功率节省。

    DRAM based refresh-free ternary CAM
    6.
    发明授权
    DRAM based refresh-free ternary CAM 有权
    基于DRAM的无刷新三元CAM

    公开(公告)号：US06331961B1

    公开(公告)日：2001-12-18

    申请号：US09591033

    申请日：2000-06-09

    Applicant: Subramani Kengeri ,  Hemraj K. Hingarh

    Inventor： Subramani Kengeri ,  Hemraj K. Hingarh

    IPC: G11C700

    CPC classification number: G11C11/406 ,  G11C15/043

    Abstract: A ternary state content addressable memory (CAM) cell that includes two DRAM cells. In addition to a port for controlling and transmitting data to the CAM, another port is exclusively used for refreshing the DRAM cells. A refresh word line is coupled to the two DRAM cells for performing DRAW cell refresh. A refresh bit line is coupled to the first of the two DRAM cells for refreshing this first DRAM cell. A refresh bit line is coupled to the second of the two DRAM cells for refreshing this second DRAM cell. Problematic power consumption and voltage swing found in a conventional CAM are overcome in the CAM. A swing line (SL) is coupled to said first and second DRAM cells and a local match line (LML) of said CAM cell, said SL having an adjustable voltage level for changing voltage swing in said LML to regulate trade-off between power consumption and speed of said CAM cell.

    Abstract translation: 包含两个DRAM单元的三态状态内容可寻址存储器（CAM）单元。 除了用于控制和发送数据到CAM的端口之外，另一个端口专门用于刷新DRAM单元。 刷新字线耦合到两个DRAM单元用于执行DRAW单元刷新。 刷新位线耦合到两个DRAM单元中的第一个用于刷新该第一DRAM单元。 刷新位线耦合到两个DRAM单元中的第二个用于刷新该第二DRAM单元。 在CAM中克服了传统CAM中出现的有问题的功耗和电压摆动。 摆动线（SL）耦合到所述第一和第二DRAM单元和所述CAM单元的局部匹配线（LML），所述SL具有用于改变所述LML中的电压摆幅的可调节电压电平，以调节功率消耗之间的权衡 和所述CAM单元的速度。

    Interleaved stitch using segmented word lines
    7.
    发明授权
    Interleaved stitch using segmented word lines 有权
    使用分段字线的交错针迹

    公开(公告)号：US6141236A

    公开(公告)日：2000-10-31

    申请号：US266175

    申请日：1999-03-10

    Applicant: Subramani Kengeri

    Inventor： Subramani Kengeri

    IPC: G11C8/14 ,  G11C11/408 ,  G11C11/4097 ,  G11C5/06

    CPC classification number: G11C8/14 ,  G11C11/408 ,  G11C11/4097

    Abstract: A word line stitch mechanism to be used in high-density DRAMs is presented herein. The word line stitch mechanism of the present invention eliminates the problem caused by using the conventional word line stitch methods of the prior art in the high-density DRAMs. In the present invention, the word lines are segmented with an space between the two adjacent word line segments. Thereafter, the contacts between the word line segments and the associated metal layers are established such that the contact overlap areas are completely adjacent to all or a portion of the spaces between the word line segments of the adjacent word lines.

    Abstract translation: 本文提出了用于高密度DRAM的字线缝合机构。 本发明的字线缝合机构消除了在高密度DRAM中使用现有技术的常规字线缝合方法所引起的问题。 在本发明中，字线被划分成两个相邻字线段之间的空间。 此后，字线段和相关联的金属层之间的接触被建立成使得接触重叠区域完全邻近相邻字线的字线段之间的空间的全部或一部分。

    High noise-margin TTL buffer circuit capable of operation with wide variation in the power supply voltage
    8.
    发明授权
    High noise-margin TTL buffer circuit capable of operation with wide variation in the power supply voltage 失效
    高噪声边缘TTL缓冲电路能够在电源电压变化很大的情况下工作

    公开(公告)号：US5612635A

    公开(公告)日：1997-03-18

    申请号：US408514

    申请日：1995-03-22

    Applicant: Raghava Madhu ,  Subramani Kengeri

    Inventor： Raghava Madhu ,  Subramani Kengeri

    IPC: H03K3/3565 ,  H03K19/0185

    CPC classification number: H03K3/3565 ,  H03K19/018521

    Abstract: A buffer circuit for converting logic signals generated by apparatus implemented in a TTL technology to logic signals processed by apparatus implemented by the CMOS technology includes an input stage (10, 11, 12, 13, 17), a voltage-control (14, 15) stage for causing the buffer circuit to vary the input voltage level required to switch the state of the buffer circuit output signal, and a hysteresis stage (16) for causing the switching of the output signal level to be different for the rising and falling edges of the input signal. The voltage-control stage (14, 15) provides a improvement in the noise margin of both the VTTL(High) switching level and the VTTL(Low) switching level.

    Abstract translation: 用于将由TTL技术实现的装置产生的逻辑信号转换成由CMOS技术实现的装置处理的逻辑信号的缓冲电路包括输入级（10,11,12,13,17），电压控制（14,15） ）级，用于使缓冲电路改变切换缓冲电路输出信号的状态所需的输入电压电平，以及用于使输出信号电平的切换对于上升沿和下降沿而不同的滞后级（16） 的输入信号。 电压控制级（14,15）提供VTTL（高）开关电平和VTTL（低）开关电平两者的噪声容限的改进。

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