公开(公告)号：US20100329055A1

公开(公告)日：2010-12-30

申请号：US12824652

申请日：2010-06-28

申请人： Kuoyuan HSU ,  Po-Hung CHEN ,  Jiann-Tseng HUANG ,  Subramani KENGERI

发明人： Kuoyuan HSU ,  Po-Hung CHEN ,  Jiann-Tseng HUANG ,  Subramani KENGERI

IPC分类号： G11C29/00 ,  G11C17/16

CPC分类号： G11C13/00 ,  G11C5/147 ,  G11C7/00 ,  G11C7/062 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/004 ,  G11C16/26 ,  G11C17/16 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0045

摘要： A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.

摘要翻译： 一种具有第一电路的电路，其被配置为接收输入电压并产生产生流过电阻器件的第一电流的第一电压和产生第二电流的第二电压; 电耦合到所述电阻装置并具有产生第三电流的第三电压的节点; 以及第二电路，被配置为产生具有指示电阻装置的逻辑状态的逻辑状态的第四电压。

公开(公告)号：US20120081165A1

公开(公告)日：2012-04-05

申请号：US12894210

申请日：2010-09-30

申请人： Jiann-Tseng HUANG ,  Sung-Chieh LIN ,  Kuoyuan HSU ,  Po-Hung CHEN

发明人： Jiann-Tseng HUANG ,  Sung-Chieh LIN ,  Kuoyuan HSU ,  Po-Hung CHEN

IPC分类号： H03L5/00 ,  H01H37/76 ,  H01L25/00

CPC分类号： H03K19/00315 ,  H03K19/018528

摘要： A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS.

摘要翻译： 高耐压逆变器电路包括：第一PMOS晶体管，其源极连接到VDDQ，漏极连接到第一节点; 第二PMOS晶体管，源极连接到第一节点，漏极连接到输出端; 第一NMOS晶体管，源极连接到VSS，漏极连接到第二节点; 第二NMOS晶体管，源极连接到第二节点，漏极连接到输出。 第一PMOS晶体管的栅极由具有VDDQ和VSS之间的电压摆幅的第一信号控制。 第一NMOS晶体管和第二PMOS晶体管的栅极由具有在VDD和VSS之间的电压摆幅的第二信号控制。 VDD低于VDDQ。 第二NMOS晶体管的栅极以大于VSS的第一电压偏置。

公开(公告)号：US20110273949A1

公开(公告)日：2011-11-10

申请号：US12774851

申请日：2010-05-06

申请人： Po-Hung CHEN ,  Sung-Chieh LIN ,  Kuoyuan HSU ,  Jiann-Tseng HUANG

发明人： Po-Hung CHEN ,  Sung-Chieh LIN ,  Kuoyuan HSU ,  Jiann-Tseng HUANG

IPC分类号： G11C17/16

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.

摘要翻译： 电路包括熔丝和感测和控制电路。 熔丝耦合在MOS晶体管和电流源节点之间。 感测和控制电路被配置为接收编程脉冲并将修改的编程信号输出到MOS晶体管的栅极，以编程保险丝。 改进的编程信号具有基于通过第一保险丝的电流的幅度的脉冲宽度。

公开(公告)号：US20120212212A1

公开(公告)日：2012-08-23

申请号：US13396235

申请日：2012-02-14

申请人： Po-Hung CHEN ,  Makoto TAKAMIYA ,  Takayasu SAKURAI

发明人： Po-Hung CHEN ,  Makoto TAKAMIYA ,  Takayasu SAKURAI

IPC分类号： G01R19/155

CPC分类号： G01R19/16519 ,  G01F3/20

摘要： In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.

摘要翻译： 在电压检测电路中，晶体管被配置为P型MOSFET，并且包括与输入端连接的源极，与接地电压端子连接的栅极和与输出端子连接的漏极。 晶体管被配置为P型MOSFET，并且包括与输出端连接的栅极和源极以及与接地端子连接的漏极。 调节晶体管的栅极宽度和栅极长度，并调整晶体管的栅极宽度和栅极长度，使得在晶体管的源极和漏极之间流动的源极 - 漏极电流变得等于在源极和漏极之间流动的源极 - 漏极电流 当施加到输入端子的电压被设置为预置触发电压时，晶体管。 该配置通过简单的配置实现了输入电压超过触发电压的检测。

公开(公告)号：US20100325364A1

公开(公告)日：2010-12-23

申请号：US12489795

申请日：2009-06-23

申请人： Po-Hung CHEN ,  Chang-Hsien TAI

发明人： Po-Hung CHEN ,  Chang-Hsien TAI

IPC分类号： G06F12/08

CPC分类号： G06F12/126 ,  G06F12/0802 ,  G06F12/0848

摘要： A cache controller, a method for controlling the cache controller, and a computing system comprising the same are provided. The computer system comprises a processor and a cache controller. The cache controller is electrically connected to the processor and comprises a first port, a second port, and at least one cache. The first port is configured to receive an address of a content, wherein a type of the content is one of instruction and data. The second port is configured to receive an information bit corresponding to the content, wherein the information bit indicates the type of the content. The at least one cache comprises at least one cache lines. Each of the cache lines comprises a content field and corresponding to an information field. The content and the information bit is stored in the content field of one of the cache lines and the corresponding information field respectively according to the information bit and the address. Thereby, instruction and data are separated in a unified cache.

摘要翻译： 提供了缓存控制器，用于控制高速缓存控制器的方法，以及包括该控制器的计算系统。 计算机系统包括处理器和高速缓存控制器。 高速缓存控制器电连接到处理器，并且包括第一端口，第二端口和至少一个高速缓存。 第一端口被配置为接收内容的地址，其中内容的类型是指令和数据之一。 第二端口被配置为接收对应于内容的信息位，其中信息位指示内容的类型。 至少一个高速缓存包括至少一个高速缓存行。 每个高速缓存行包括与信息字段对应的内容字段。 内容和信息位分别根据信息位和地址存储在高速缓存线之一的内容字段和对应的信息字段中。 因此，指令和数据在统一缓存中分离。

公开(公告)号：US20120057423A1

公开(公告)日：2012-03-08

申请号：US12877646

申请日：2010-09-08

申请人： Po-Hung CHEN ,  Chin-Huang WANG ,  Yen-Chieh HUANG ,  Sung-Chieh LIN ,  Kuoyuan (Peter) HSU

发明人： Po-Hung CHEN ,  Chin-Huang WANG ,  Yen-Chieh HUANG ,  Sung-Chieh LIN ,  Kuoyuan (Peter) HSU

IPC分类号： G11C17/16

CPC分类号： G11C17/165

摘要： Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.

摘要翻译： 一些实施例涉及具有以行和列，多个位线和多个字线布置的多个eFuse存储器单元的存储器阵列。 列包括位线选择器，耦合到位线选择器的位线和多个eFuse存储器单元。 该列的eFuse存储单元包括PMOS晶体管和eFuse。 PMOS晶体管的漏极耦合到eFuse的第一端。 PMOS晶体管的栅极耦合到字线。 PMOS晶体管的源极耦合到列的位线。

公开(公告)号：US20120086495A1

公开(公告)日：2012-04-12

申请号：US12900650

申请日：2010-10-08

申请人： Po-Hung CHEN ,  Kuoyuan (Peter) HSU ,  David YEN ,  Sung-Chieh LIN

发明人： Po-Hung CHEN ,  Kuoyuan (Peter) HSU ,  David YEN ,  Sung-Chieh LIN

IPC分类号： H03L5/00

CPC分类号： H03K3/356165

摘要： An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.

摘要翻译： 第一反相器的输入被配置为用作输入节点。 第一反相器的输出耦合到第二反相器的输入端。 第二反相器的输出被配置为用作输出节点。 第三反相器的输入耦合到第一反相器的输入端。 第一NMOS晶体管的栅极耦合到第三反相器的输出端。 第一NMOS晶体管的漏极耦合到第二反相器。 第一NMOS晶体管的源极被配置为用作电平输入节点。 当输入节点被配置为接收低逻辑电平时，输出节点被配置为接收由电平输入节点处的电压电平提供的电压电平。