公开(公告)号：US20080254779A1

公开(公告)日：2008-10-16

申请号：US12089011

申请日：2006-09-25

Applicant: Sung-Ho Hwang ,  Myoung-Gyu Son ,  Kyung-Hoon Kim ,  Sang-Man Bak

Inventor： Sung-Ho Hwang ,  Myoung-Gyu Son ,  Kyung-Hoon Kim ,  Sang-Man Bak

IPC: H04M3/42 ,  H04B7/216

CPC classification number: H04W4/18 ,  H04W4/14 ,  H04W88/184

Abstract: A method for converting a SMS sent through a mobile communication network into a SMS or MMS in a previously registered format includes the steps of: receiving a SMS from a certain sending subscriber, determining whether the corresponding sending subscriber is subscribed to a SMS converting service, then converting the SMS into a previously registered format in case the sending subscriber is subscribed to the SMS converting service, and then sending the converted message to a designated receiving terminal.

Abstract translation: 用于将通过移动通信网络发送的SMS以预先注册的格式转换成SMS或MMS的方法包括以下步骤：从某个发送用户接收SMS，确定对应的发送用户是否订阅了SMS转换服务， 然后在发送订户订阅SMS转换服务的情况下将SMS转换成先前注册的格式，然后将转换的消息发送到指定的接收终端。

公开(公告)号：US07428286B2

公开(公告)日：2008-09-23

申请号：US11026583

申请日：2004-12-30

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H04L7/00

CPC classification number: H03K5/1565 ,  H03L7/0814 ,  H03L7/089

Abstract: The present invention is directed to a duty cycle correction apparatus that can be implemented in a small size, and is capable of performing a phase lock more rapidly, and reducing the amount of current being consumed, and to a method thereof. The duty cycle correction apparatus in accordance with the present invention for use in a semiconductor memory device includes a delay line unit for delaying a first clock signal to produce a first delayed clock signal; an output tap unit for delaying the first delayed clock signal by a pulse width of a first logic state of the first clock signal under the control of a toss control signal derived from a second clock signal; and a phase mixer for mixing the clock signal from the output tap unit and one of the first and second clock signals.

Abstract translation: 本发明涉及一种占空比校正装置，其能够以小尺寸实现，并且能够更快地执行锁相，并且减少被消耗的电流量及其方法。 根据本发明的用于半导体存储器件的占空比校正装置包括延迟线单元，用于延迟第一时钟信号以产生第一延迟时钟信号; 输出抽头单元，用于在由第二时钟信号导出的折腾控制信号的控制下将第一延迟时钟信号延迟第一时钟信号的第一逻辑状态的脉冲宽度; 以及用于混合来自输出抽头单元的时钟信号和第一和第二时钟信号之一的相位混合器。

公开(公告)号：US07365564B2

公开(公告)日：2008-04-29

申请号：US11525951

申请日：2006-09-25

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03K19/003

CPC classification number: G06F1/10 ,  H04L25/0298

Abstract: An apparatus for controlling an on die termination (ODT) includes a counting unit for receiving an external clock signal and a delay locked loop (DLL) clock signal, and counting the toggle number of each of external clock signal and the DLL clock signal from a preset number; a comparing control unit for comparing the counted toggle number of the external clock signal with that of the DLL clock signal in response to an ODT command signal, and outputting an ODT enable signal for controlling the ODT based on the compared result.

Abstract translation: 用于控制管芯端接（ODT）的装置包括：计数单元，用于接收外部时钟信号和延迟锁定环（DLL）时钟信号;以及计数来自外部时钟信号和DLL时钟信号的触发数量 预设号码 比较控制单元，用于响应于ODT命令信号来比较外部时钟信号的计数触发数与DLL时钟信号的计数触发数，并根据比较结果输出用于控制ODT的ODT使能信号。

公开(公告)号：US07362158B2

公开(公告)日：2008-04-22

申请号：US11429297

申请日：2006-05-05

Applicant: Tae-Hyeong Park ,  Kook-Chul Moon ,  Il-Gon Kim ,  Chul-Ho Kim ,  Kyung-Hoon Kim ,  Ho-Suk Maeng

Inventor： Tae-Hyeong Park ,  Kook-Chul Moon ,  Il-Gon Kim ,  Chul-Ho Kim ,  Kyung-Hoon Kim ,  Ho-Suk Maeng

IPC: H03L5/00

CPC classification number: H03K3/356165

Abstract: A level shifter and a display device having the same are provided. In a level shifter, a first transistor includes a gate electrode receiving a first driving voltage, and a source electrode receiving an input signal through an input terminal. A second transistor includes a drain electrode receiving the first driving voltage, and a source electrode electrically connected to a drain electrode of the first transistor through a first node. A third transistor includes a source electrode receiving a second driving voltage, a drain electrode electrically connected to a gate electrode of the second transistor through a second node, and a gate electrode receiving the input signal. A fourth transistor includes a drain electrode receiving the first driving voltage, a gate electrode electrically connected to the drain electrode of the first transistor through the first node, and a source electrode electrically connected to the drain electrode of the third transistor through the second node. An inverter inverts a signal outputted from the second node to apply the inverted signal to an output terminal.

Abstract translation: 提供了一种电平移位器和具有该电平移位器的显示装置。 在电平移位器中，第一晶体管包括接收第一驱动电压的栅极电极和通过输入端子接收输入信号的源电极。 第二晶体管包括接收第一驱动电压的漏电极和通过第一节点电连接到第一晶体管的漏电极的源电极。 第三晶体管包括接收第二驱动电压的源电极，通过第二节点电连接到第二晶体管的栅电极的漏电极和接收输入信号的栅电极。 第四晶体管包括接收第一驱动电压的漏电极，通过第一节点电连接到第一晶体管的漏电极的栅电极和通过第二节点电连接到第三晶体管的漏电极的源电极。 反相器将从第二节点输出的信号反相，将反相信号施加到输出端。

公开(公告)号：US20080080263A1

公开(公告)日：2008-04-03

申请号：US11819801

申请日：2007-06-29

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: G11C7/00 ,  G11C7/10 ,  G11C8/00

CPC classification number: G11C7/22 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/222

Abstract: A semiconductor memory device includes a first clock input unit for generating a first clock signal based on a signal at an intersection of a system clock signal and an inverted system clock signal; a second input unit for generating a second clock signal based on a signal at an intersection of the system clock signal and a reference signal; a third input unit for generating a third clock signal based on a signal at an intersection of the inverted system clock signal and the reference signal; a delay unit for generating a delay clock signal by delaying the first clock signal in response to a delay control signal; and a clock delay control unit for generating the delay control signal in response to a phase difference between the second clock signal and the delay clock signal or a phase difference between the third clock signal and the delay clock signal.

Abstract translation: 半导体存储器件包括：第一时钟输入单元，用于基于系统时钟信号和反相系统时钟信号的交点处的信号产生第一时钟信号; 第二输入单元，用于基于系统时钟信号和参考信号的交点处的信号产生第二时钟信号; 第三输入单元，用于基于反相系统时钟信号和参考信号的交点处的信号产生第三时钟信号; 延迟单元，用于通过响应于延迟控制信号延迟所述第一时钟信号来产生延迟时钟信号; 以及时钟延迟控制单元，用于响应于第二时钟信号和延迟时钟信号之间的相位差或第三时钟信号和延迟时钟信号之间的相位差产生延迟控制信号。

公开(公告)号：US07323900B2

公开(公告)日：2008-01-29

申请号：US11320664

申请日：2005-12-30

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03K17/16

CPC classification number: H04L25/0278 ,  G01R31/31715 ,  G11C29/02 ,  G11C29/022 ,  G11C29/50008 ,  G11C2207/2254

Abstract: A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value until the test signal is equal to the reference signal; an impedance measuring unit for measuring an impedance of the test pad based on the adjusted value to output the test signal; an impedance adjusting unit for adjusting an impedance of a data I/O pad to have an impedance value corresponding to the adjusted value outputted when the test signal is equal to the reference signal; an impedance control unit for controlling the comparing unit so that the adjusted value is outputted when the test signal is equal to the reference signal; and a reference signal control unit for adjusting a voltage level of the reference signal.

公开(公告)号：US20070126467A1

公开(公告)日：2007-06-07

申请号：US11322283

申请日：2005-12-29

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03K19/003

CPC classification number: G11C29/02 ,  G01R31/31715 ,  G01R31/318511 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  H04L25/0278 ,  H04L25/0298

Abstract: An on die termination (ODT) test device includes: a control unit for selectively activating a plurality of pull-up signals and a plurality of pull-down signals by performing a logic operation to an ODT control signal for controlling a resistor of a termination terminal, an off chip driver (OCD) control signal for adjusting an impedance of an output terminal, a plurality of ODT test signals for measuring a termination resistance of the termination terminal and a plurality of ODT signals having a different resistance; and a pull-up/pull-down unit for selectively driving a plurality of pull-up drivers and a plurality of pull-down drivers according to the pull-up signals and the pull-down signals in order to output a corresponding resistance of the output terminal at a read operation mode.

Abstract translation: 芯片终端（ODT）测试装置包括：控制单元，用于通过对ODT控制信号执行逻辑操作来选择性地激活多个上拉信号和多个下拉信号，以控制终端终端 ，用于调整输出端子的阻抗的芯片外驱动器（OCD）控制信号，用于测量终端终端的终端电阻的多个ODT测试信号和具有不同电阻的多个ODT信号; 以及上拉/下拉单元，用于根据上拉信号和下拉信号选择性地驱动多个上拉驱动器和多个下拉驱动器，以输出相应的电阻 输出端子处于读操作模式。

公开(公告)号：US20070070717A1

公开(公告)日：2007-03-29

申请号：US11319615

申请日：2005-12-29

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: G11C7/06

CPC classification number: G11C7/1051 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1069 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/105 ,  G11C2207/2254

Abstract: An apparatus for comparing inputted signals by removing an offset voltage during adjusting an output impedance of a semiconductor memory device, includes a voltage comparator for comparing a first input signal applied to its positive input node with a second input signal applied to its negative input node to output a first output signal to its positive output node and its second output signal to a negative output node; a switched capacitive unit for removing an offset voltage occurred in the positive input node, the negative input node, the positive output node and the negative output node of the voltage comparator; and a latch unit for latching the first output signal and the second output signal.

Abstract translation: 一种用于在调整半导体存储器件的输出阻抗期间去除偏移电压来比较输入信号的装置，包括电压比较器，用于将施加于其正输入节点的第一输入信号与施加到其负输入节点的第二输入信号进行比较， 将第一输出信号输出到其正输出节点并将其第二输出信号输出到负输出节点; 用于去除电压比较器的正输入节点，负输入节点，正输出节点和负输出节点中发生的偏移电压的开关电容单元; 以及用于锁存第一输出信号和第二输出信号的锁存单元。

公开(公告)号：US20070069779A1

公开(公告)日：2007-03-29

申请号：US11478191

申请日：2006-06-30

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/0805 ,  H03L7/087

Abstract: A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.

Abstract translation: 延迟锁定环通过使用具有比DLL输出时钟更高级的相位的输出时钟来增加延迟锁定环的操作余量。 时钟延迟补偿块接收外部时钟信号从而产生第一多时钟和第二多时钟。 相位控制块将第一多时钟与第二多个时钟进行比较，以产生控制移位操作的相位控制信号。 多相延迟控制块基于相位控制信号执行移位操作，以控制时钟延迟补偿块。

公开(公告)号：US20070069777A1

公开(公告)日：2007-03-29

申请号：US11478082

申请日：2006-06-30

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/0805

Abstract: A Delay Locked Loop (DLL) driver control circuit is capable of reducing an amount of current consumption by preventing the output of unnecessary clocks. The DLL driver control circuit includes a DLL driver for driving a DLL clock and a DLL driver controller for generating a control signal to control an operation of the DLL driver in response to a signal having information associated with an active mode. The DLL driver controller is provided with a counter for counting the DLL clock to produce a count a setting value having a plurality of bits and generating an activated equal signal if the two values are the same, and an SR latch for accepting the equal signal and the signal having the information associated with the active mode to provide the control signal.

Abstract translation: 延迟锁定环（DLL）驱动器控制电路能够通过防止不必要的时钟的输出来减少电流消耗的量。 DLL驱动器控制电路包括用于驱动DLL时钟的DLL驱动器和用于产生用于响应于具有与活动模式相关联的信息的信号来控制DLL驱动程序的操作的DLL驱动器控制器。 DLL驱动器控制器设置有用于对DLL时钟进行计数以产生具有多个位的设置值的计数器，并且如果两个值相同则产生激活的等信号;以及SR锁存器，用于接受相等的信号和 所述信号具有与所述活动模式相关联的信息以提供所述控制信号。