公开(公告)号：US20070257694A1

公开(公告)日：2007-11-08

申请号：US11775472

申请日：2007-07-10

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G01R31/02

CPC分类号： G01R31/2851 ,  G01R31/31715 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318563 ,  G01R31/31919

摘要： An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together. The scan distributor and collector circuits can be formed in core circuits (704). The core circuits then can be connected to other core circuits and functional circuits with simple connections to the parallel scan circuits through the scan distributor and collector circuits.

摘要翻译： 具有并行扫描路径（824-842,924-942）的集成电路（70）包括一对或一对扫描分配器（800,900）和扫描收集器（844,944）电路。 扫描路径将激励测试数据应用于集成电路上的功能电路（702），并从功能电路接收响应测试数据。 扫描分配器电路（800）从外围接合焊盘（802）接收串行测试数据，并将其分配到每个并行扫描路径。 扫描收集器电路（844）从并行扫描路径收集测试数据并将其应用于外围接合焊盘（866）。 这使得更长的并行扫描路径能够连接到功能电路。 扫描分配器和集电极电路可以分别串联连接以提供并行连接到更平行的扫描路径。 此外，多路复用器电路（886,890）可以选择性地将成对的扫描分配器和集电极电路连接在一起。 扫描分配器和集电极电路可以形成在核心电路（704）中。 然后，核心电路可以通过扫描分配器和集电极电路与并行扫描电路的简单连接连接到其他核心电路和功能电路。

公开(公告)号：US20070145997A1

公开(公告)日：2007-06-28

申请号：US11565979

申请日：2006-12-01

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G01R31/26

CPC分类号： G01R31/3177 ,  G01R31/2884 ,  G01R31/31721 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/318511 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318572 ,  G01R31/318575 ,  G01R31/318577 ,  G01R31/318583 ,  G01R31/3187 ,  G06F1/3234

摘要： Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

摘要翻译： 晶片上晶片的测试是通过以下方式实现的： （1）向测试人员提供使用同时双向收发器电路外部传送JTAG测试信号的能力;（2）使用同时双向收发器电路在晶片上提供外部传送JTAG测试信号的能力，以及（3）提供连接 测试器的双向收发器电路与晶片上所选择的组或晶片上的所有芯片之间的机制，用于通信JTAG信号。

公开(公告)号：US20060242520A1

公开(公告)日：2006-10-26

申请号：US11278064

申请日：2006-03-30

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G01R31/28

CPC分类号： G01R31/31721 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318575

摘要： A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

摘要翻译： Scan-BIST架构适用于低功耗Scan-BIST架构。 发电机102，压实机106和控制器110保持与已知技术相同。 已知的Scan-BIST架构和低功率Scan-BIST架构之间的变化包括将已知扫描路径修改为扫描路径502，以插入扫描路径A 506，B 508和C 510，以及插入适配器电路 504在控制器110和扫描路径502之间的控制路径114中。

公开(公告)号：US20060156112A1

公开(公告)日：2006-07-13

申请号：US11292643

申请日：2005-12-02

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G01R31/28

CPC分类号： G01R31/3172 ,  G01R31/31701 ,  G01R31/31705 ,  G01R31/31712 ,  G01R31/31713 ,  G01R31/31722 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318364 ,  G01R31/318555 ,  G01R31/318558 ,  G06F11/267

摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the invention include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

摘要翻译： 本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。 总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。 总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。 本发明的其它方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。

公开(公告)号：US20050270858A1

公开(公告)日：2005-12-08

申请号：US11198064

申请日：2005-08-05

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G01R31/3185 ,  G06F1/04 ,  G11C5/00 ,  H04J3/06 ,  H04L7/00

CPC分类号： G06F13/4291 ,  G01R31/31725 ,  G01R31/31726 ,  G01R31/318536 ,  G01R31/318594 ,  G06F1/04 ,  G06F1/06 ,  H04B1/18 ,  H04J3/0644 ,  H04L7/0008

摘要： Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

公开(公告)号：US20050246597A1

公开(公告)日：2005-11-03

申请号：US11177663

申请日：2005-07-07

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G06F11/22 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/00 ,  G06F11/267 ,  G06F11/30 ,  G06F13/00 ,  G06F13/38

CPC分类号： G01R31/318555 ,  G01R31/31855 ,  G01R31/318569 ,  G01R31/318572 ,  G06F11/221

摘要： A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EQM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded for observation and test of variable width data buses and variable width signature analysis.

摘要翻译： 用于观察连接多个集成电路（10,12）的总线（14,16,18）上的数据的数字总线监视器包括存储器缓冲器（30），旁路寄存器（34），测试端口（38）和输出控制电路 （42,46）由事件限定模块（EQM）（32）控制。 响应于匹配条件，当集成电路（10,12）以速度继续运行时，EQM（32）可以对输入数据执行各种测试。 可以级联多个数字总线监视器（20,22），用于观察和测试可变宽度数据总线和可变宽度签名分析。

公开(公告)号：US20050204236A1

公开(公告)日：2005-09-15

申请号：US11096399

申请日：2005-04-01

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G01R31/3185 ,  G01N15/08 ,  G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318508 ,  G01R31/318555

摘要： This disclosure describes a test architecture for accessing IP core test wrappers within an IC and for accessing the wrappers using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper basically resides at the boundary of the core and provides a way to test the core and the interconnections between cores. While IEEE P1500 is standardizing the wrapper, it leaves the architectural arrangement of multiple and hierarchical wrappers within an IC up to the users of the P1500 standard.

摘要翻译： 本公开描述了用于访问IC内的IP核测试包装器并且使用链接指令寄存器（LIR）访问包装器的测试架构。 正在开发IEEE P1500标准，通过称为包装器的测试结构提供对这些单独内核的测试访问。 包装器基本上位于核心的边界，并提供了一种测试核心和核心之间互连的方法。 虽然IEEE P1500正在标准化封装，但它将IC内的多层和分层封装的架构布局留给了P1500标准的用户。

公开(公告)号：US20050204225A1

公开(公告)日：2005-09-15

申请号：US11051707

申请日：2005-02-04

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G01R31/28

CPC分类号： G01R31/31713 ,  G01R31/28 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318594 ,  G06F1/12 ,  G06F13/287 ,  G06F13/4282 ,  H03K19/017509

摘要： The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

摘要翻译： 本公开描述了使用JTAG TAP的TMS和TCK终端作为通用串行输入/输出（I / O）总线的新颖方法和装置。 根据本公开，TAP的TMS终端被用作时钟信号，并且TCK终端被用作双向数据信号以允许串行通信之间发生; （1）IC和外部控制器，（2）在第一和第二IC之间，或（3）IC内的第一和第二核心电路之间。

公开(公告)号：US20050204217A1

公开(公告)日：2005-09-15

申请号：US11051696

申请日：2005-02-04

申请人： Lee Whetsel ,  Alan Hales

发明人： Lee Whetsel ,  Alan Hales

IPC分类号： G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/3193

摘要： Today large system-on-chips (SOC) are designed using predefined circuit functions commonly referred to as cores. In some cases, multiple instances of the same core may be implemented within an SOC to achieve greater functional performance of the SOC. Having multiple cores of the same type in an SOC lends itself to parallel testing of the cores. This disclosure describes an improved core DFT architecture that facilitates parallel testing of same type cores within an SOC.

摘要翻译： 今天，大型片上系统（SOC）使用通常称为内核的预定义电路功能进行设计。 在一些情况下，可以在SOC内实现相同核心的多个实例以实现SOC的更大的功能性能。 在SOC中具有相同类型的多个核可以自己进行核的并行测试。 本公开描述了一种改进的核心DFT架构，其有助于SOC内的同类型核的并行测试。

公开(公告)号：US20050050414A1

公开(公告)日：2005-03-03

申请号：US10962950

申请日：2004-10-12

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318561 ,  G01R31/318563 ,  G01R31/318572

摘要： An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

摘要翻译： 集成电路可以具有多个核心电路，每个核心电路具有在IEEE标准1149.1中定义的测试访问端口。 这些端口的访问和控制是一个测试链接模块。 集成电路上的测试访问端口可以以一个测试链接模块来控制对多个辅助测试链接模块和测试访问端口的访问的层次结构。 每个次级测试链接模块依次也可以控制对三级测试链接模块和测试访问端口的访问。 测试链接模块也可用于仿真。