公开(公告)号：US20110072410A1

公开(公告)日：2011-03-24

申请号：US12788651

申请日：2010-05-27

Applicant: Joo Chul Lee ,  Tae Man Han

Inventor： Joo Chul Lee ,  Tae Man Han

IPC: G06F9/44

CPC classification number: G06F8/35 ,  G06F8/10

Abstract: Provided are an EMF model synchronization method and system. The system calculates a weight based on a hierarchy for an object identifier in a changed model, when the change of the model occurs in an EMF model which has an XML element path as an attribute. The system accumulates the calculated weight to a sum of weights. When the sum of weights becomes greater than the threshold value, the system simultaneously updates all models which are changed until the sum of weights becomes greater than the threshold value, thereby synchronizing change contents. As a hierarchy of an identifier changed on an XML path becomes higher, the weight is determined to have a larger value.

Abstract translation: 提供了EMF模型同步方法和系统。 当在具有XML元素路径作为属性的EMF模型中发生模型的改变时，系统基于改变的模型中的对象标识符的层次来计算权重。 系统将计算出的权重累加为权重之和。 当权重之和变得大于阈值时，系统同时更新所有改变的模型，直到权重之和变得大于阈值，从而同步改变内容。 由于在XML路径上更改的标识符的层次结构变得更高，所以权重被确定为具有较大的值。

公开(公告)号：US20110019474A1

公开(公告)日：2011-01-27

申请号：US12898070

申请日：2010-10-05

Applicant: Jin-Man Han ,  Aaron Yip

Inventor： Jin-Man Han ,  Aaron Yip

IPC: G11C16/06

CPC classification number: G11C29/846 ,  G11C29/82 ,  G11C2216/30

Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.

Abstract translation: 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个列的存储块。 每个列包括位线和位线上的多个存储单元。 多个列包括多组常规列和多组冗余列。 该装置还包括多个数据锁存器。 每个数据锁存器被配置为存储从相应的一组常规列读取的数据。 该装置还包括多个冗余数据锁存器。 每个冗余数据锁存器被配置为存储从相应的一组冗余列读取的数据。 该装置还包括多路复用器，其被配置为选择性地从多个数据锁存器和多个冗余数据锁存器输出数据。

公开(公告)号：US20110013451A1

公开(公告)日：2011-01-20

申请号：US12893328

申请日：2010-09-29

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

Abstract: A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.

Abstract translation: 具有单级单元和多级单元的非易失性存储器阵列。 在一个实施例中，单电平和多电平电池沿着每个位线交替。 一个替代实施例沿着位线和字线交替单电层和多电平单元，使得没有单层单元与字线或位线方向上的另一单级单元相邻。

公开(公告)号：US20100135084A1

公开(公告)日：2010-06-03

申请号：US12698833

申请日：2010-02-02

Applicant: Xiaojun Yu ,  Jin-man Han

Inventor： Xiaojun Yu ,  Jin-man Han

IPC: G11C16/06 ,  G11C5/02 ,  G11C16/04

CPC classification number: G11C16/08

Abstract: The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that is substantially the same as the threshold voltage of the string driver during memory cell program operations. In some embodiments, the regulator may comprise a cascode-connected pair of transistors. Methods of manufacturing and operating the apparatus and systems are also described.

Abstract translation: 本文描述的装置和系统可以包括耦合到本地字线的多个存储器单元和包括耦合到多个传输晶体管的调节器和字符串驱动器的字线驱动电路。 调节器可以包括调节器晶体管，其具有在存储器单元程序操作期间与串驱动器的阈值电压基本相同的阈值电压。 在一些实施例中，调节器可以包括共源共栅连接的晶体管对。 还描述了制造和操作装置和系统的方法。

公开(公告)号：US07719888B2

公开(公告)日：2010-05-18

申请号：US12141159

申请日：2008-06-18

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C16/04

CPC classification number: G11C11/5642 ,  G11C16/0483

Abstract: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to selected access lines for sensing selected memory cells. The method also includes applying a dynamic pass voltage to unselected access lines while the sensing voltages are applied.

Abstract translation: 本公开包括用于操作存储器单元的方法，设备，模块和系统。 一种方法实施例包括将感测电压施加到用于感测所选存储单元的所选择的接入线 该方法还包括在施加感测电压的同时向未选择的接入线施加动态通过电压。

公开(公告)号：US20100027558A1

公开(公告)日：2010-02-04

申请号：US12577831

申请日：2009-10-13

Applicant: Tae Man HAN ,  You Hyeon JEONG ,  Heesung CHAE ,  Dong Won KIM ,  Jun Hwa LEE

Inventor： Tae Man HAN ,  You Hyeon JEONG ,  Heesung CHAE ,  Dong Won KIM ,  Jun Hwa LEE

IPC: H04L12/413

CPC classification number: H04W74/02 ,  H04L12/413 ,  H04L12/417 ,  H04W74/0816

Abstract: Provided is a distributed and asynchronous implicit token carrier sense multiple access/collision avoidance (CSMA/CA) protocol guaranteeing quality of service for both real time and non-real time traffic. The implicit token CSMA/CA protocol allocates a band in an entire bandwidth to voice traffic and allows the remaining bands to be used for data traffic. The implicit token CSMA/CA protocol includes applying a token passing protocol to transmit voice traffic in real time by having a band in an entire bandwidth allocated using a predetermined data frame and applying a CSMA/CA mechanism to transmit data traffic in non-real time by employing remaining bands not allocated to the voice traffic using another predetermined data frame.

Abstract translation: 提供了一种分布式和异步隐含令牌载波侦听多路访问/冲突避免（CSMA / CA）协议，保证实时和非实时流量的服务质量。 隐性令牌CSMA / CA协议将整个带宽中的频带分配给语音业务，并允许剩余频带用于数据业务。 隐含令牌CSMA / CA协议包括通过使用预定数据帧分配整个带宽中的频带并且以非实时的方式应用CSMA / CA机制来发送数据业务来应用令牌传递协议来实时传输话音业务 通过使用未分配给语音业务的剩余频带，使用另一预定数据帧。

公开(公告)号：US07656740B2

公开(公告)日：2010-02-02

申请号：US11702261

申请日：2007-02-05

Applicant: Xiaojun Yu ,  Jin-man Han

Inventor： Xiaojun Yu ,  Jin-man Han

IPC: G11C8/00

CPC classification number: G11C16/08

Abstract: The apparatus and systems comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that is substantially the same as the threshold voltage of the string driver during memory cell program operations. The regulator may comprise a cascode-connected pair of transistors. Methods of manufacturing and operating the apparatus and systems are also described.

Abstract translation: 该装置和系统包括耦合到本地字线的多个存储器单元和包括耦合到多个传输晶体管和串驱动器的调节器的字线驱动电路。 调节器可以包括调节器晶体管，其具有在存储器单元程序操作期间与串驱动器的阈值电压基本相同的阈值电压。 调节器可以包括共源共栅连接的晶体管对。 还描述了制造和操作装置和系统的方法。

公开(公告)号：US20090262591A1

公开(公告)日：2009-10-22

申请号：US12497998

申请日：2009-07-06

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C16/0483 ,  G11C16/12 ,  G11C2207/229

Abstract: The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency.

Abstract translation: 本发明提供了方法和装置。 NAND闪存器件以第一频率接收命令和地址信号，并以大于第一频率的第二频率接收数据信号。

公开(公告)号：US07548459B2

公开(公告)日：2009-06-16

申请号：US11511451

申请日：2006-08-29

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C11/03

CPC classification number: G11C8/20 ,  G06F11/1068 ,  G11C8/10 ,  G11C29/808 ,  G11C2029/0411

Abstract: A method, apparatus and system providing a memory device having an array of cells which may be selectively designated for either error correction code use or redundancy cell use.

Abstract translation: 一种提供存储器件的方法，装置和系统，该存储器件具有可选择性地指定用于纠错码使用或冗余单元使用的单元阵列。

公开(公告)号：US20090147553A1

公开(公告)日：2009-06-11

申请号：US12200922

申请日：2008-08-28

Applicant: Byoung Woo Ryu ,  Chong Eun Kim ,  Dong Seong Oh ,  Jeong Man Han

Inventor： Byoung Woo Ryu ,  Chong Eun Kim ,  Dong Seong Oh ,  Jeong Man Han

IPC: H02M7/04

CPC classification number: H02M3/33592 ,  H02M3/3374 ,  H02M2001/007 ,  Y02B70/1433 ,  Y02B70/1475

Abstract: A direct current (DC) power supply for varying an output voltage according to a load current variation is disclosed. The DC power supply includes an alternating current(AC)/DC conversion unit converting commercial AC power into DC power, a DC/DC conversion unit converting a voltage level of the DC power and outputting output power, and a control unit controlling conversion of the voltage level of the fed-back DC power according to a variation in a load current of the output power from the DC/DC conversion unit.

Abstract translation: 公开了一种用于根据负载电流变化改变输出电压的直流（DC）电源。 直流电源包括将商用交流电转换为直流电力的交流（AC）/ DC转换单元，转换直流电力的电压电平并输出输出电力的DC / DC转换单元，以及控制单元， 根据来自DC / DC转换单元的输出功率的负载电流的变化，反馈DC电力的电压电平。