公开(公告)号：US08595423B2

公开(公告)日：2013-11-26

申请号：US13546944

申请日：2012-07-11

申请人： Jin-Man Han

发明人： Jin-Man Han

IPC分类号： G06F13/00

CPC分类号： G11C16/10 ,  G11C8/08 ,  G11C16/3495 ,  G11C2216/14

摘要： Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure.

摘要翻译： 公开了诸如涉及闪存装置的方法和装置。 一种这样的方法包括将存储器单元上的数据存储在包括字线上的多个字线和多个存储器单元的存储器块上。 字线包括一个或多个底边字线，一个或多个顶边字线，以及底边和顶边字线之间的中间字线。 数据首先存储在中间字线上的存储单元上。 然后，数据的剩余部分（如果有的话）被存储在底部边缘字线和/或顶部边缘字线上的存储器单元上。 该方法通过防止底部或顶部边缘字线上的存储器单元的过早故障来增加闪存的寿命，这可能更容易发生故障。

公开(公告)号：US08179721B2

公开(公告)日：2012-05-15

申请号：US12893328

申请日：2010-09-29

申请人： Jin-Man Han

发明人： Jin-Man Han

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

摘要： A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.

摘要翻译： 具有单级单元和多级单元的非易失性存储器阵列。 在一个实施例中，单电平和多电平电池沿着每个位线交替。 一个替代实施例沿着位线和字线交替单电层和多电平单元，使得没有单层单元与字线或位线方向上的另一单级单元相邻。

公开(公告)号：US08072816B2

公开(公告)日：2011-12-06

申请号：US12478877

申请日：2009-06-05

申请人： Jin-Man Han ,  Aaron Yip

发明人： Jin-Man Han ,  Aaron Yip

IPC分类号： G11C16/06

CPC分类号： G11C8/08 ,  G06F12/0246 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3427 ,  G11C29/76 ,  G11C29/82 ,  Y02D10/13

摘要： A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

摘要翻译： 非易失性存储器件具有将特定存储器块的页面重新分配给其他块，以便增加减少的干扰并增加可靠性。 包含来自期望的存储器块的重新分配的页面的每个重新分配块被耦合到字线驱动器。 这些字线驱动器具有全局字线的一部分作为输入。 期望的字线驱动器通过来自块解码器的适当选择信号和适当的全局字线上的指示来选择。 这将导致字线驱动程序在要重新分配的页面访问期望块时生成本地字线。

公开(公告)号：US07949821B2

公开(公告)日：2011-05-24

申请号：US12138137

申请日：2008-06-12

申请人： Jin-Man Han

发明人： Jin-Man Han

IPC分类号： G06F13/00 ,  G06F13/28 ,  G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C8/08 ,  G11C16/3495 ,  G11C2216/14

摘要： Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure.

摘要翻译： 公开了诸如涉及闪存装置的方法和装置。 一种这样的方法包括将存储器单元上的数据存储在包括字线上的多个字线和多个存储器单元的存储器块上。 字线包括一个或多个底边字线，一个或多个顶边字线，以及底边和顶边字线之间的中间字线。 数据首先存储在中间字线上的存储单元上。 然后，数据的剩余部分（如果有的话）被存储在底部边缘字线和/或顶部边缘字线上的存储器单元上。 该方法通过防止底部或顶部边缘字线上的存储器单元的过早故障来增加闪存的寿命，这可能更容易发生故障。

公开(公告)号：US07688630B2

公开(公告)日：2010-03-30

申请号：US12370810

申请日：2009-02-13

申请人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

发明人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

摘要翻译： 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

公开(公告)号：US20090190400A1

公开(公告)日：2009-07-30

申请号：US12417224

申请日：2009-04-02

申请人： Jin-Man Han

发明人： Jin-Man Han

IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

摘要： A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.

摘要翻译： 具有单级单元和多级单元的非易失性存储器阵列。 在一个实施例中，单电平和多电平电池沿着每个位线交替。 一个替代实施例沿着位线和字线交替单电层和多电平单元，使得没有单层单元与字线或位线方向上的另一单级单元相邻。

公开(公告)号：US20070268775A1

公开(公告)日：2007-11-22

申请号：US11436352

申请日：2006-05-18

申请人： Jin-Man Han

发明人： Jin-Man Han

IPC分类号： G11C8/00 ,  G11C11/34 ,  G11C16/04

CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C16/0483 ,  G11C16/12 ,  G11C2207/229

摘要： The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency.

摘要翻译： 本发明提供了方法和装置。 NAND闪存器件以第一频率接收命令和地址信号，并以大于第一频率的第二频率接收数据信号。

公开(公告)号：US07006398B1

公开(公告)日：2006-02-28

申请号：US10977309

申请日：2004-10-29

申请人： Sei-Seung Yoon ,  Jin-Man Han ,  Seong-Ook Jung

发明人： Sei-Seung Yoon ,  Jin-Man Han ,  Seong-Ook Jung

IPC分类号： G11C11/00

CPC分类号： H01L27/11 ,  G11C11/39

摘要： A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.

摘要翻译： 本文公开了一种包括用于解析由存储器单元产生的数据信号的读出放大器的感测电路。 感测电路包括用于接收数据信号的位线，耦合到位线并被配置为对位线预充电的第一预充电器件，用于提供耦合到位线的偏置并被配置为提供 偏置到位线，以及被配置为至少一个预定电平的参考节点。 在一个实施例中，预定电平等于诸如地电位的低电位，而在另一实施例中等于诸如V DD的高电位。 一个或多个开关装置允许激活或去激活预充电装置，允许将位线预充电到特定电位，感测电路快速而准确地确定逻辑状态“1”或“0”是否为 应用于位线。

公开(公告)号：US6097649A

公开(公告)日：2000-08-01

申请号：US088426

申请日：1998-06-01

申请人： Paul M-Bhor Chiang ,  Jin-Man Han ,  Hung-Mao Lin

发明人： Paul M-Bhor Chiang ,  Jin-Man Han ,  Hung-Mao Lin

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A method and structure for a refresh operation with a low voltage of logic high in a computer memory structure is provided. The method and system includes first the precharging of a plurality of bit lines and a plurality of complementary bit lines to a voltage higher than the reference voltage. Then at least one of a plurality of word lines and at least one of a plurality of reference word lines are selected. Next, the sense amplifier is activated such that either the plurality of bit lines or the plurality of complementary bit lines discharges to a voltage of logic low. This discharge creates a voltage difference between the plurality of bit lines and the plurality of complementary bit lines. The resulting voltage on the bit lines is restored to the memory cells on the selected word lines. Then, the plurality of bit lines and the plurality of complementary bit lines are restored to the reference voltage. This method and structure allows the use of a logic high voltage lower than 2.0 V without compromising the reliability of the sense amplifier. The implementation of the method and structure of the present invention is cost effective and practical for most if not all DRAM applications.

摘要翻译： 提供了一种用于在计算机存储器结构中具有高逻辑高电压的刷新操作的方法和结构。 该方法和系统首先将多个位线和多个互补位线预充电到高于参考电压的电压。 然后，选择多个字线和至少一个参考字线中的至少一个。 接下来，感测放大器被激活，使得多个位线或多个互补位线放电到逻辑低电压。 该放电在多个位线和多个互补位线之间产生电压差。 位线上产生的电压恢复到所选字线上的存储单元。 然后，将多条位线和多条互补位线恢复到参考电压。 该方法和结构允许使用低于2.0V的逻辑高电压，而不损害读出放大器的可靠性。 本发明的方法和结构的实现对于大多数（如果不是全部）DRAM应用是成本有效的和实用的。

公开(公告)号：US5812466A

公开(公告)日：1998-09-22

申请号：US724798

申请日：1996-10-02

申请人： Jung-Hwa Lee ,  Jin-Man Han ,  Dong-Il Seo

发明人： Jung-Hwa Lee ,  Jin-Man Han ,  Dong-Il Seo

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/70

摘要： The present invention relates to a semiconductor memory device incorporating a column redundancy circuit using a decoded fuse. The column redundancy circuit is capable of designating a repaired address during a parallel test mode of memory operation when an address input is a "don't care," and it is particularly useful in a multiple input/output memory architecture which uses one column select per I/O line. The column redundancy circuit includes: transmitting means comprised of the data input/output lines for transmitting the data of the memory cell; column decoder and input/output control circuits connected to the transmitting means and decoding a column address input to input data; a circuit connected to the transmitting means and outputting a given signal to the column decoder and input/output control circuits in response to a plurality of output signals output from fuses and a signal for controlling the transmitting means; a plurality of decoded fuse circuits, the levels of which are determined by one fuse connected to the circuit; multiplexers for selectively transmitting data from one of the data input/output lines to a specific data bus line among a plurality of data bus lines; and a decoding circuit which receives the outputs of the decoded fuse circuits and generates a redundancy signal.

摘要翻译： 本发明涉及一种结合使用解码保险丝的列冗余电路的半导体存储器件。 当地址输入为“无关”时，列冗余电路能够在存储器操作的并行测试模式下指定修复的地址，并且在使用一列选择的多输入/输出存储器架构中特别有用 每个I / O线。 列冗余电路包括：发送装置，包括用于发送存储单元的数据的数据输入/输出线; 列解码器和连接到发送装置的输入/输出控制电路，并且将输入的列地址解码为输入数据; 连接到发送装置的电路，响应于从保险丝输出的多个输出信号和用于控制发送装置的信号，将给定信号输出到列解码器和输入/输出控制电路; 多个解码熔丝电路，其电平由连接到电路的一个熔丝确定; 多路复用器，用于选择性地将数据从数据输入/输出线之一发送到多条数据总线之间的特定数据总线; 以及解码电路，其接收解码的熔丝电路的输出并产生冗余信号。