公开(公告)号：US07659170B2

公开(公告)日：2010-02-09

申请号：US11620406

申请日：2007-01-05

Applicant: Christoph Schwan ,  Manfred Horstmann ,  Martin Gerhardt ,  Markus Forseberg

Inventor： Christoph Schwan ,  Manfred Horstmann ,  Martin Gerhardt ,  Markus Forseberg

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L29/665

Abstract: By recessing the isolation structure of a transistor prior to silicidation, the series resistance may be reduced due to the increased amount of metal silicide formed in the vicinity of the isolation structure. By recessing the isolation structure prior to the formation of the gate electrode, an increased degree of poly wrap around may be obtained, thereby increasing the effective channel width.

Abstract translation: 通过在硅化之前使晶体管的隔离结构凹陷，由于在隔离结构附近形成的金属硅化物的量增加，串联电阻可能会降低。 通过在形成栅电极之前使隔离结构凹陷，可以获得增加的聚环绕的程度，从而增加有效沟道宽度。

公开(公告)号：US07563731B2

公开(公告)日：2009-07-21

申请号：US11739279

申请日：2007-04-24

Applicant: Christoph Schwan ,  Manfred Horstmann ,  Kai Frohberg ,  Rolf Stephan

Inventor： Christoph Schwan ,  Manfred Horstmann ,  Kai Frohberg ,  Rolf Stephan

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  Y10S438/902

Abstract: By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.

Abstract translation: 通过在形成第一层高应力电介质材料之后增加晶体管形貌，可以添加额外的应力材料，从而有效地增加应力介电材料的整个层厚度。 可以基于相应的占位符结构或伪栅极来实现器件形貌的相应增加，其中可以使用完全确定的栅极图案化工艺，或者可以采用纳米压印技术。 因此，在一些说明性实施例中，可以基于公认的工艺技术获得应变的显着增加。

公开(公告)号：US07381624B2

公开(公告)日：2008-06-03

申请号：US11177214

申请日：2005-07-08

Applicant: Andy Wei ,  Thorsten Kammler ,  Michael Raab ,  Manfred Horstmann

Inventor： Andy Wei ,  Thorsten Kammler ,  Michael Raab ,  Manfred Horstmann

IPC: H01L21/20

CPC classification number: H01L29/7833 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76254 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659

Abstract: By direct bonding of two crystalline semiconductor layers of different crystallographic orientation and/or material composition and/or internal strain, bulk-like hybrid substrates may be formed, thereby providing the potential for forming semiconductor devices in accordance with a single transistor architecture on the hybrid substrate.

Abstract translation: 通过直接键合具有不同晶体取向和/或材料组成和/或内部应变的两个晶体半导体层，可以形成块状混合衬底，从而提供根据混合物上的单晶体管结构形成半导体器件的潜力 基质。

公开(公告)号：US20080081486A1

公开(公告)日：2008-04-03

申请号：US11739279

申请日：2007-04-24

Applicant: Christoph Schwan ,  Manfred Horstmann ,  Kai Frohberg ,  Rolf Stephan

Inventor： Christoph Schwan ,  Manfred Horstmann ,  Kai Frohberg ,  Rolf Stephan

IPC: H01L21/31

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  Y10S438/902

Abstract: By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.

Abstract translation: 通过在形成第一层高应力电介质材料之后增加晶体管的形貌，可添加额外的应力材料，从而有效地增加应力介电材料的整个层厚度。 可以基于相应的占位符结构或伪栅极来实现器件形貌的相应增加，其中可以使用完全确定的栅极图案化工艺，或者可以采用纳米压印技术。 因此，在一些说明性实施例中，可以基于公认的工艺技术获得应变的显着增加。

公开(公告)号：US20080079039A1

公开(公告)日：2008-04-03

申请号：US11736622

申请日：2007-04-18

Applicant: Christoph Schwan ,  Joe Bloomquist ,  Kai Frohberg ,  Manfred Horstmann

Inventor： Christoph Schwan ,  Joe Bloomquist ,  Kai Frohberg ,  Manfred Horstmann

IPC: H01L21/326 ,  H01L29/76

CPC classification number: H01L29/7833 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/66772

Abstract: A method of forming a field effect transistor comprises providing a substrate comprising, at least on a surface thereof, a first semiconductor material. A recess is formed in the substrate. The recess is filled with a second semiconductor material. The second semiconductor material has a different lattice constant than the first semiconductor material. A gate electrode is formed over the recess filled with the second semiconductor material.

Abstract translation: 形成场效应晶体管的方法包括提供至少在其表面上包括第一半导体材料的衬底。 在基板上形成凹部。 凹部填充有第二半导体材料。 第二半导体材料具有与第一半导体材料不同的晶格常数。 在填充有第二半导体材料的凹部上形成栅电极。

公开(公告)号：US20080026531A1

公开(公告)日：2008-01-31

申请号：US11684211

申请日：2007-03-09

Applicant: Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

Inventor： Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.

Abstract translation: 形成场效应晶体管的方法包括提供半导体衬底，栅电极形成在半导体衬底上。 在栅电极附近形成至少一个空腔。 应变产生元件形成在至少一个空腔中。 应变产生元件包括包含第一化学元素和第二化学元素的复合材料。 应变产生元件的第一部分中的第一化学元素的浓度与应变产生元件的第一部分中的第二化学元素的浓度之间的第一浓度比不同于第二浓度比， 的应变产生元件的第二部分中的第一化学元素和第二应变产生元件中的第二化学元素的浓度。

公开(公告)号：US20080003783A1

公开(公告)日：2008-01-03

申请号：US11624276

申请日：2007-01-18

Applicant: Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

Inventor： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

IPC: H01L21/36

CPC classification number: H01L29/7848 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method of smoothening a surface of a semiconductor structure comprises exposing the surface of the semiconductor structure to a reactant. A chemical reaction between a material of the semiconductor structure and the reactant is performed. In the chemical reaction, a layer of a reaction product is formed on at least a portion of the surface of the semiconductor structure. The layer of the reaction product is selectively and completely removed.

Abstract translation: 使半导体结构的表面平滑化的方法包括将半导体结构的表面暴露于反应物。 进行半导体结构材料与反应物之间的化学反应。 在化学反应中，在半导体结构的表面的至少一部分上形成反应产物层。 反应产物层被选择性地完全除去。

公开(公告)号：US20070281472A1

公开(公告)日：2007-12-06

申请号：US11622088

申请日：2007-01-11

Applicant: Patrick Press ,  Thomas Feudel ,  Joe Bloomquist ,  Manfred Horstmann

Inventor： Patrick Press ,  Thomas Feudel ,  Joe Bloomquist ,  Manfred Horstmann

IPC: H01L21/44

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/7624 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: By performing a laser-based or flash-based anneal process after silicidation, the degree of dopant activation with reduced diffusion activity may be accomplished, while the characteristics of the metal silicide may be improved or the complexity for manufacturing the same may be reduced.

Abstract translation: 通过在硅化后进行基于激光或闪光的退火工艺，可以实现具有降低的扩散活性的掺杂剂活化程度，同时可以改善金属硅化物的特性或者可以降低其制造的复杂性。

公开(公告)号：US07297994B2

公开(公告)日：2007-11-20

申请号：US11072142

申请日：2005-03-04

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

IPC: H10L29/00 ,  H01L29/80

CPC classification number: H01L21/823807 ,  H01L29/1033 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/6659

Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

Abstract translation: 在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。 根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与常规器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。 此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。 可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。

公开(公告)号：US20070254444A1

公开(公告)日：2007-11-01

申请号：US11608591

申请日：2006-12-08

Applicant: Joe Bloomquist ,  Peter Javorka ,  Manfred Horstmann ,  Gert Burbach

Inventor： Joe Bloomquist ,  Peter Javorka ,  Manfred Horstmann ,  Gert Burbach

IPC: H01L29/80 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1203 ,  H01L29/7843

Abstract: By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.

Abstract translation: 通过在逻辑区域和存储区域中选择性地执行预非晶化注入工艺，可以避免在应力覆盖层和位错缺陷之间的相互作用的负面影响或至少在存储区域中显着降低，从而提高存储器的产量和稳定性 地区