DATA REORDERING METHOD AND APPARATUS THEREOF
    31.
    发明公开

    公开(公告)号:US20240244007A1

    公开(公告)日:2024-07-18

    申请号:US18414774

    申请日:2024-01-17

    申请人: MEDIATEK INC.

    IPC分类号: H04L47/34 H04L47/2408

    CPC分类号: H04L47/34 H04L47/2408

    摘要: A reordering method performed by a receiving apparatus is provided. The receiving apparatus may receive a first PPDU from a transmitting apparatus, wherein the first PPDU includes a plurality of MPDUs, and the MPDUs correspond to the same BA window. The receiving apparatus may determine a traffic that each of the MPDUs belongs to according to an MPDU identification, wherein traffics that the plurality of MPDUs belonging to include a first traffic and a second traffic which is different from the first traffic. The receiving apparatus may perform a reordering operation for the MPDUs belonging to the first traffic, and a reordering operation for the MPDUs belonging to the second traffic, respectively. The receiving apparatus may transmit a BA frame in response to the first PPDU to the transmitting apparatus, wherein the BA frame includes information for indicating whether the MPDUs in the first PPDU have been successfully received.

    ELECTROSTATIC DISCHARGE (ESD) PROTECTION STRUCTURE

    公开(公告)号:US20240243120A1

    公开(公告)日:2024-07-18

    申请号:US18544764

    申请日:2023-12-19

    申请人: MEDIATEK INC.

    IPC分类号: H01L27/02

    CPC分类号: H01L27/027

    摘要: Electrostatic discharge (ESD) protection structures are provided. A first N-type well region is formed over a P-type semiconductor substrate. First P-type well region and second N-type well region are formed over the first N-type well region. A plurality of first device areas are formed over the first P-type well region. Each first device area includes a plurality of P-type fins extending in a first direction. The P-type fins are divided into a plurality of first groups in each of the first device areas. A second device area is formed over the first P-type well region, and includes a plurality of N-type fins extending in the first direction and surrounded by the first device areas. When an ESD event is present, an ESD current flows sequentially through the P-type fins, the first P-type well region and the N-type fins.

    METHOD FOR ADAPTIVELY ADJUSTING STATE TRANSITION TIME IN PERIPHERAL COMPONENT INTERCONNECT EXPRESS SYSTEM TO ENHANCE OVERALL PERFORMANCE, AND ASSOCIATED APPARATUS

    公开(公告)号:US20240241569A1

    公开(公告)日:2024-07-18

    申请号:US18096545

    申请日:2023-01-12

    申请人: MEDIATEK INC.

    发明人: Sheng-Ya Tung

    IPC分类号: G06F1/3296 G06F1/08

    CPC分类号: G06F1/3296 G06F1/08

    摘要: A method for adaptively adjusting state transition time in a Peripheral Component Interconnect (PCI) Express (PCIe) system and associated apparatus such as a root complex (RC) device and an endpoint device are provided. The method may include: toggling a clock request signal on a signal path coupled between the RC device and the endpoint device based on a request from the RC device or on a request from the endpoint device, wherein when the clock request signal toggles, the endpoint device transits from a first state to a second state; and toggling a reference clock signal from the RC device at a timing determined according to a training parameter among at least one predetermined parameter which is set dependent on at least one of the factors: a transition time, a restoration delay, a latency tolerance report (LTR) and a bias state, after the clock request signal toggles.

    Optimization of Scratchpad Memory Allocation for Heterogeneous Devices Using A Cooperative Compiler Framework

    公开(公告)号:US20240231910A9

    公开(公告)日:2024-07-11

    申请号:US17969397

    申请日:2022-10-19

    申请人: MediaTek Inc.

    发明人: Chi-Wei Wang

    IPC分类号: G06F9/50 G06F8/41

    CPC分类号: G06F9/5016 G06F8/441

    摘要: A system allocates scratchpad memory (SPM) to heterogeneous devices for neural network computing. The system executes the operations of a global optimization manager. The global optimization manager receives compilation states from compilers, which compile corresponding subgraphs of a neural network model into corresponding subcommands that run on the heterogeneous devices. The global optimization manager unifies records of a same object across different ones of the compilation states, and allocates the SPM to the subgraphs according to the unified records of the compilation states.

    THRESHOLD VOLTAGE SENSOR AND A CHIP USING THE THRESHOLD VOLTAGE SENSOR

    公开(公告)号:US20240223142A1

    公开(公告)日:2024-07-04

    申请号:US18326136

    申请日:2023-05-31

    申请人: MEDIATEK INC.

    IPC分类号: H03F3/45

    摘要: A low-cost and high-accuracy threshold voltage (Vth) sensor is shown. In addition to a current mirror implemented by an operational amplifier and two metal-oxide-semiconductor field-effect transistors (MOSFETs), the Vth sensor uses an active device and a diode-connected MOSFET. The active device is provided to determine a constant current that is mirrored from the first MOSFET to the second MOSFET of the current mirror. The diode-connected MOSFET is coupled between the drain terminal of the second MOSFET and the ground terminal. The constant current flows through the diode-connected MOSFET to generate an output voltage that contains information about a threshold voltage (Vth) of a MOSFET.