Blower fan
    31.
    发明授权
    Blower fan 有权
    鼓风机

    公开(公告)号:US08757990B2

    公开(公告)日:2014-06-24

    申请号:US13405347

    申请日:2012-02-26

    Abstract: A blower fan including a motor having a rotating shaft, a bracket, a fan housing having a cavity, a fan wheel, and fan blades. The motor is disposed on the fan housing via the bracket. An extended portion of the rotating shaft extends into the cavity of the fan housing and connects with the fan wheel. The fan blades are disposed on the rotating shaft and between the motor and the fan housing. On the casing of the motor is disposed with air vents. The bracket forms an annular side wall. A cavity is formed inside the annular side wall. The annular side wall is outfitted with air outlets which are connected with the cavity of the annular side wall and the fan blades are disposed in the cavity.

    Abstract translation: 一种风扇,包括具有旋转轴的电动机,支架,具有空腔的风扇壳体,风扇叶轮和风扇叶片。 电机通过支架设置在风扇外壳上。 旋转轴的延伸部分延伸到风扇壳体的空腔中并与风扇轮连接。 风扇叶片设置在旋转轴上,电机和风扇外壳之间。 在电机的外壳上配有通气孔。 支架形成环形侧壁。 在环形侧壁内形成空腔。 环形侧壁配有与环形侧壁的空腔连接的空气出口,风扇叶片设置在空腔中。

    Device System Structure Based On Hybrid Orientation SOI and Channel Stress and Preparation Method Thereof
    32.
    发明申请
    Device System Structure Based On Hybrid Orientation SOI and Channel Stress and Preparation Method Thereof 审中-公开
    基于混合取向SOI和沟道应力的器件系统结构及其制备方法

    公开(公告)号:US20130221412A1

    公开(公告)日:2013-08-29

    申请号:US13811269

    申请日:2012-09-19

    Abstract: The present invention provides a device system structure based on hybrid orientation SOI and channel stress and a preparation method thereof. According to the preparation method provided in the present invention, first, a (100)/(110) global hybrid orientation SOI structure is prepared; then, after epitaxially growing a relaxed silicon-germanium layer and strained silicon layer sequentially on the global hybrid orientation SOI structure, an (110) epitaxial pattern window is formed; then, after epitaxially growing a (110) silicon layer and a non-relaxed silicon-germanium layer at the (110) epitaxial pattern window, a surface of the patterned hybrid orientation SOI structure is planarized; then, an isolation structure for isolating devices is formed; and finally, a P-type high-voltage device structure is prepared in a (110) substrate portion, an N-type high-voltage device structure and/or low voltage device structures are prepared in the (100) substrate portion. In this manner, a carrier mobility is improved, Rdson of a high-voltage device is reduced, and performance of devices are improved, thereby facilitating further improvement of integration and reduction of power consumption.

    Abstract translation: 本发明提供了一种基于混合取向SOI和沟道应力的器件系统结构及其制备方法。 根据本发明提供的制备方法,首先制备(100)/(110)全局杂化取向SOI结构; 然后,在全局混合取向SOI结构上顺序生长松弛的硅 - 锗层和应变硅层之后,形成(110)外延图形窗口; 然后,在(110)外延图形窗口外延生长(110)硅层和非松弛硅 - 锗层之后,将图案化混合取向SOI结构的表面平面化; 然后形成用于隔离装置的隔离结构; 最后,在(110)衬底部分中制备P型高电压器件结构,在(100)衬底部分中制备N型高压器件结构和/或低电压器件结构。 以这种方式,提高了载流子迁移率,降低了高电压装置的Rdson,提高了器件性能,从而进一步提高了集成度和降低了功耗。

    Method of NiSiGe epitaxial growth by introducing Al interlayer
    33.
    发明授权
    Method of NiSiGe epitaxial growth by introducing Al interlayer 失效
    通过引入Al中间层的NiSiGe外延生长方法

    公开(公告)号:US08501593B2

    公开(公告)日:2013-08-06

    申请号:US13260757

    申请日:2011-07-25

    Abstract: The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reaction between Ni layer and SiGe material of SiGe layer to form NiSiGe material. Due to the barrier effect of Al interlayer, NiSiGe layer features a single crystal structure, a flat interface with SiGe substrate and a thickness of up to 0.3 nm, significantly enhancing interface performance.

    Abstract translation: 本发明公开了一种通过引入Al中间层的NiSiGe外延生长方法,包括在SiGe层的表面上沉积Al薄膜,随后在Al薄膜上沉积Ni层,然后在Ni之间进行退火处理 SiGe层的SiGe材料,形成NiSiGe材料。 由于Al中间层的阻挡效应,NiSiGe层具有单晶结构,与SiGe衬底的平坦界面,厚度可达0.3nm,显着提高了界面性能。

    ICING DETECTOR PROBE AND ICING DETECTOR WITH THE SAME
    34.
    发明申请
    ICING DETECTOR PROBE AND ICING DETECTOR WITH THE SAME 有权
    检测器探测器及其检测器

    公开(公告)号:US20130105631A1

    公开(公告)日:2013-05-02

    申请号:US13809934

    申请日:2011-06-30

    CPC classification number: B64D15/20

    Abstract: An icing detector probe includes three sections arranged sequentially along the direction of air flow, namely, a first section, a second section and a third section. The shape of the outer surface of the first section is suitable for collecting droplets in the air flow. The shape of the outer surface of the second section is suitable for full decelerating and releasing latent heat of large droplets during their movements. The outer surface of the third section is suitable for icing of large droplets. The probe detects icing by distinguishing and identify large droplets icing. The probe effectively detects types of traditional icing, thus being helpful for exact detection of icing thickness. An icing detector including said icing detector probe is also provided.

    Abstract translation: 结冰检测器探头包括沿空气流动方向依次布置的三个部分,即第一部分,第二部分和第三部分。 第一部分的外表面的形状适合于在空气流中收集液滴。 第二部分的外表面的形状适合于在其运动期间完全减速和释放大液滴的潜热。 第三部分的外表面适用于大液滴的结冰。 探测器通过识别和识别大型液滴结冰来检测结冰。 探头有效地检测传统结冰的类型,有助于精确检测结冰厚度。 还提供了包括所述结冰检测器探针的结冰检测器。

    Hybrid material inversion mode GAA CMOSFET
    35.
    发明授权
    Hybrid material inversion mode GAA CMOSFET 有权
    混合材料反演模式GAA CMOSFET

    公开(公告)号:US08350298B2

    公开(公告)日:2013-01-08

    申请号:US12810619

    申请日:2010-02-11

    Abstract: A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects.

    Abstract translation: Ge和Si混合材料反转模式GAA(Gate-All-Around)CMOSFET包括具有第一沟道的PMOS区域,具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在反相模式下,器件具有混合材料,GAA结构,具有跑道形,高k栅介质层和金属栅极,从而实现高载流子迁移率,防止多晶硅栅极耗尽和短沟道效应。

    Illumination Methods And Systems For Improving Image Resolution Of Imaging Systems
    36.
    发明申请
    Illumination Methods And Systems For Improving Image Resolution Of Imaging Systems 审中-公开
    用于改善成像系统图像分辨率的照明方法和系统

    公开(公告)号:US20120289832A1

    公开(公告)日:2012-11-15

    申请号:US13517960

    申请日:2010-12-21

    Applicant: Miao Zhang Hui Hu

    Inventor: Miao Zhang Hui Hu

    CPC classification number: G02B21/0012 A61B8/54 A61B90/20 A61B90/30 G02B21/06

    Abstract: Method and systems for improving resolution of imaging systems, such as a microscope or a medical ultrasonic scanner, are provided. The resolution of the microscope is improved by reducing direct illumination of unrelated regions of an object under examination. According to an aspect of the present invention, a method is provided to reduce the direct illumination of the unrelated regions in a detectable region such as a cone of light that otherwise could generate substantial noises. In another aspect of the invention, a method is provided that focuses the illumination beams such that the width of the projected beam spot is narrowed, preventing the generation of a large amount of noise. In particular, the width of the illumination beam is narrowed such that the size of the projected illumination beam is smaller than the field of view of the microscope. In another aspect of the invention, a system according to the principles of the present invention is provided, wherein the illumination beam of light is such arranged that the overlap of the path of the illumination beam of light and the detectable region is reduced.

    Abstract translation: 提供了用于提高诸如显微镜或医用超声波扫描仪的成像系统的分辨率的方法和系统。 通过减少被检查物体的不相关区域的直接照射来改善显微镜的分辨率。 根据本发明的一个方面,提供了一种方法来减少可检测区域(例如光锥的不相关区域)的直接照明,否则可能会产生实质的噪声。 在本发明的另一方面,提供了一种聚焦照明光束使得投射的光斑的宽度变窄的方法,防止产生大量的噪声。 特别地,照明光束的宽度变窄,使得投影照明光束的尺寸小于显微镜的视场。 在本发明的另一方面,提供了根据本发明的原理的系统,其中照明光束被布置成使得照明光束和可检测区域的路径的重叠减少。

    HYBRID MATERIAL INVERSION MODE GAA CMOSFET
    37.
    发明申请
    HYBRID MATERIAL INVERSION MODE GAA CMOSFET 有权
    混合材料反相模式GAA CMOSFET

    公开(公告)号:US20110248354A1

    公开(公告)日:2011-10-13

    申请号:US12810619

    申请日:2010-02-11

    Abstract: A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects.

    Abstract translation: Ge和Si混合材料反转模式GAA(Gate-All-Around)CMOSFET包括具有第一沟道的PMOS区域,具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在反相模式下,器件具有混合材料,GAA结构,具有跑道形,高k栅介质层和金属栅极,从而实现高载流子迁移率,防止多晶硅栅极耗尽和短沟道效应。

    Push/push latch
    38.
    发明授权
    Push/push latch 有权
    推/推闩锁

    公开(公告)号:US09523222B2

    公开(公告)日:2016-12-20

    申请号:US14119693

    申请日:2012-08-08

    Abstract: The instant disclosure provides a push latch having a pivotally mounted blocking hammer including a head with a lever arm extending away from the head to a counter-weight. Under normal operating conditions, the hammer is held in an inert/balanced condition. Under such normal conditions, a portion of the hammer head may be in periodic contact with a resin of tacky character defining a bumper to aid in dampening vibration. Upon the occurrence of a high impact force, the rotational force provided by the counterweight is sufficient to cause the hammer to rotate into blocking relation relative to the latching mechanism so as to prevent unlatching. In the rotated condition, the counterweight may be in contact with an optional resin of tacky character defining a bumper to reduce rebound action.

    Abstract translation: 本公开提供了具有枢转安装的阻塞锤的推动闩锁,其包括具有远离头部延伸到对重的杠杆臂的头部。 在正常操作条件下,锤子保持在惰性/平衡状态。 在这种正常条件下,锤头的一部分可以与形成保险杠的具有粘性的树脂周期性地接触以帮助减振。 在发生高冲击力时,由配重提供的旋转力足以使锤子相对于锁定机构转动成阻塞关系,以防止解锁。 在旋转状态下,配重可以与限定保险杠的可选择的粘性树脂接触以减少回弹动作。

    SILICON-GERMANIUM HETEROJUNCTION TUNNEL FIELD EFFECT TRANSISTOR AND PREPARATION METHOD THEREOF
    39.
    发明申请
    SILICON-GERMANIUM HETEROJUNCTION TUNNEL FIELD EFFECT TRANSISTOR AND PREPARATION METHOD THEREOF 有权
    硅锗绝缘隧道场效应晶体管及其制备方法

    公开(公告)号:US20140199825A1

    公开(公告)日:2014-07-17

    申请号:US13811268

    申请日:2012-09-19

    Abstract: A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects. The preparation method according to the present invention has a simple process, which is compatible with the CMOS process and is applicable to mass industrial production.

    Abstract translation: 提供硅/锗(SiGe)异质结隧道场效应晶体管(TFET)及其制备方法,其中器件的源极区域在硅锗(GeGe)或Ge区域上制造,漏极区域 在Si区域中制造器件,从而在确保低OFF状态电流的同时获得高导通状态电流。 本地Ge氧化和浓缩技术用于在某些地区实施高Ge含量的硅锗绝缘体(SGOI)或锗绝缘体(GOI)。 在高Ge含量的SGOI或GOI中,Ge含量可控制在50%〜100%之间。 另外,膜厚可以从5nm到20nm的范围内控制,便于实现器件工艺。 在SiGe或Ge和Si的氧化和浓缩过程中,在SiGe或Ge和Si之间形成具有梯度Ge含量的SiGe异质结结构,从而消除缺陷。 根据本发明的制备方法具有与CMOS工艺兼容的简单工艺,并且适用于大规模工业生产。

    PUSH/PUSH LATCH
    40.
    发明申请
    PUSH/PUSH LATCH 有权
    推/拉锁

    公开(公告)号:US20140145453A1

    公开(公告)日:2014-05-29

    申请号:US14119693

    申请日:2012-08-08

    Abstract: The instant disclosure provides a push latch having a pivotally mounted blocking hammer including a head with a lever arm extending away from the head to a counter-weight. Under normal operating conditions, the hammer is held in an inert/balanced condition. Under such normal conditions, a portion of the hammer head may be in periodic contact with a resin of tacky character defining a bumper to aid in dampening vibration. Upon the occurrence of a high impact force, the rotational force provided by the counterweight is sufficient to cause the hammer to rotate into blocking relation relative to the latching mechanism so as to prevent unlatching. In the rotated condition, the counterweight may be in contact with an optional resin of tacky character defining a bumper to reduce rebound action.

    Abstract translation: 本公开提供了具有枢转安装的阻塞锤的推动闩锁,其包括具有远离头部延伸到对重的杠杆臂的头部。 在正常操作条件下,锤子保持在惰性/平衡状态。 在这种正常条件下,锤头的一部分可以与形成保险杠的具有粘性的树脂周期性地接触以帮助减振。 在发生高冲击力时,由配重提供的旋转力足以使锤子相对于锁定机构转动成阻塞关系,以防止解锁。 在旋转状态下,配重可以与限定保险杠的可选择的粘性树脂接触以减少回弹动作。

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