公开(公告)号：US06377941B1

公开(公告)日：2002-04-23

申请号：US09338450

申请日：1999-06-22

Applicant: Andre Steimle ,  Pascal Tannhof

Inventor： Andre Steimle ,  Pascal Tannhof

IPC: G06F1518

CPC classification number: G06K9/6271 ,  G06N3/063 ,  G06N3/08

Abstract: A method of achieving automatic learning of an input vector presented to an artificial neural network (ANN) formed by a plurality of neurons, using the K nearest neighbor (KNN) mode. Upon providing an input vector to be learned to the ANN, a Write component operation is performed to store the input vector components in the first available free neuron of the ANN. Then, a Write category operation is performed by assigning a category defined by the user to the input vector. Next, a test is performed to determine whether this category matches the categories of the nearest prototypes, i.e. which are located at the minimum distance. If it matches, this first free neuron is not engaged. Otherwise, it is engaged by assigning the matching category to it. As a result, the input vector becomes the new prototype with the matching category associated thereto. Further described is a circuit which automatically retains the first free neuron of the ANN for learning.

Abstract translation: 使用K个最近邻（KNN）模式，实现由多个神经元形成的人造神经网络（ANN）的输入向量的自动学习的方法。 在向ANN提供要学习的输入向量时，执行写分量操作以将输入矢量分量存储在ANN的第一可用游离神经元中。 然后，通过将由用户定义的类别分配给输入向量来执行写类别操作。 接下来，执行测试以确定该类别是否与最近的原型的类别匹配，即位于最小距离的类别。 如果它匹配，这个第一个自由神经元没有被使用。 否则，通过将匹配类别分配给它来进行。 结果，输入向量成为与其相关联的匹配类别的新原型。 进一步描述了自动保留ANN的第一自由神经元进行学习的电路。

公开(公告)号：US5023478A

公开(公告)日：1991-06-11

申请号：US493079

申请日：1990-03-13

Applicant: Gerard Boudon ,  Pierre Mollier ,  Seiki Ogura ,  Dominique Omet ,  Pascal Tannhof ,  Franck Wallart

Inventor： Gerard Boudon ,  Pierre Mollier ,  Seiki Ogura ,  Dominique Omet ,  Pascal Tannhof ,  Franck Wallart

IPC: H03K19/086 ,  H03F1/30 ,  H03F3/30 ,  H03K17/56 ,  H03K17/567 ,  H03K17/66 ,  H03K19/01 ,  H03K19/013 ,  H03K19/018 ,  H03K19/08

CPC classification number: H03K19/013 ,  H03F1/308 ,  H03F3/3008 ,  H03F3/3071 ,  H03K17/667

Abstract: The present invention relates to fast complementary emitter follower drivers/buffers to be used in either a CMOS or pure complementary bipolar environment. The output driver (22) comprises top NPN and bottom PNP output transistors (T1, T2) with a common output node (N) connected therebetween. A terminal (15) is connected to the said output node (N) where the output signal (VOUT) is available. The pair of bipolar output transistors is biased between the first and second supply voltages (VH, GND). The output driver is provided with a voltage translator circuit (S) connected between the base nodes (B1, B2) of the output transistors (T1, T2). Logic signals (IN1, IN2), supplied by a preceding driving circuit (21), are applied to said base nodes. According to the invention, the voltage translator circuit (S) comprises two diodes (D1, D2) connected in series, preferably implemented with a main bipolar transistor having a junction shorted by a diode connected transistor to form a Darlington-like configuration. As a result, the voltage shift VS between the base nodes is selected to have the said output transistors operating at an operating point which ensures minimum delay and power consumption. In a typical bipolar technology, VS is made to be approximately equal to 1.5V. Additional features comprise the connection of a capacitor (C) between the base nodes and resistances (R1, R2) to the base nodes. The preceding driving circuit may be a CMOS logic gate or an ECL logic circuit.