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14 条记录 (耗时 0.021 秒)

    Complementary emitter follower drivers
    1.
    发明授权
    Complementary emitter follower drivers 失效
    互补射极跟随器驱动器

    公开(公告)号：US5023478A

    公开(公告)日：1991-06-11

    申请号：US493079

    申请日：1990-03-13

    申请人： Gerard Boudon ,  Pierre Mollier ,  Seiki Ogura ,  Dominique Omet ,  Pascal Tannhof ,  Franck Wallart

    发明人： Gerard Boudon ,  Pierre Mollier ,  Seiki Ogura ,  Dominique Omet ,  Pascal Tannhof ,  Franck Wallart

    IPC分类号： H03K19/086 ,  H03F1/30 ,  H03F3/30 ,  H03K17/56 ,  H03K17/567 ,  H03K17/66 ,  H03K19/01 ,  H03K19/013 ,  H03K19/018 ,  H03K19/08

    CPC分类号： H03K19/013 ,  H03F1/308 ,  H03F3/3008 ,  H03F3/3071 ,  H03K17/667

    摘要： The present invention relates to fast complementary emitter follower drivers/buffers to be used in either a CMOS or pure complementary bipolar environment. The output driver (22) comprises top NPN and bottom PNP output transistors (T1, T2) with a common output node (N) connected therebetween. A terminal (15) is connected to the said output node (N) where the output signal (VOUT) is available. The pair of bipolar output transistors is biased between the first and second supply voltages (VH, GND). The output driver is provided with a voltage translator circuit (S) connected between the base nodes (B1, B2) of the output transistors (T1, T2). Logic signals (IN1, IN2), supplied by a preceding driving circuit (21), are applied to said base nodes. According to the invention, the voltage translator circuit (S) comprises two diodes (D1, D2) connected in series, preferably implemented with a main bipolar transistor having a junction shorted by a diode connected transistor to form a Darlington-like configuration. As a result, the voltage shift VS between the base nodes is selected to have the said output transistors operating at an operating point which ensures minimum delay and power consumption. In a typical bipolar technology, VS is made to be approximately equal to 1.5V. Additional features comprise the connection of a capacitor (C) between the base nodes and resistances (R1, R2) to the base nodes. The preceding driving circuit may be a CMOS logic gate or an ECL logic circuit.

    BICMOS logic circuit with full swing operation
    2.
    发明授权
    BICMOS logic circuit with full swing operation 失效
    BICMOS逻辑电路全方位运行

    公开(公告)号：US5010257A

    公开(公告)日：1991-04-23

    申请号：US493014

    申请日：1990-03-13

    申请人： Gerard Boudon ,  Pierre Mollier ,  Jean-Paul Nuez ,  Ieng Ong ,  Pascal Tannhof ,  Franck Wallart

    发明人： Gerard Boudon ,  Pierre Mollier ,  Jean-Paul Nuez ,  Ieng Ong ,  Pascal Tannhof ,  Franck Wallart

    IPC分类号： H03K17/567 ,  H03K5/007 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/0944

    CPC分类号： H03K19/0136 ,  H03K19/09448 ,  H03K5/007

    摘要： According to the present invention, a CMOS interface circuit (C2) similar to a latch made by two CMOS cross coupled inverters (INV1, INV2) is placed directly on the output node (14) of conventional BICMOS logic circuit (11) operating alone in a partial swing mode. This latch is made of four FETs P5, P6, N8, N9 cross-coupled in a conventional way with the feedback loop connected to said output node (14). The partial voltage swing (VBE to VH-VBE) naturally given by the output bipolar transistors (T1, T2) mounted in a push pull configuration is reinforced to full swing (GND to VH) by the latch at the end of each transition. The state of the output node if forced by the latch because of the high driving capability due to the presence of said output bipolar transistors (T1, T2). As a result, the improved BICMOS logic circuit (D2) has an output signal (S) that ranges within the desired full swing voltage at the output terminal (15). It is a characteristic of this embodiment that the structure of CMOS interface (C2) is always independent of the logic function implemented in the conventional BICMOS logic circuit (11). More generally, the CMOS interface circuit may have various physical implementations, however, it is always comprised of CMOS FETs and it becomes active at least in one of the GND to VBE or (VH-BE) to VH range.

    Chip to chip information bit transmission process and device
    5.
    发明授权
    Chip to chip information bit transmission process and device 失效
    芯片到芯片信息位传输过程和设备

    公开(公告)号：US4539680A

    公开(公告)日：1985-09-03

    申请号：US556803

    申请日：1983-12-01

    申请人： Gerard Boudon ,  Pierre Mollier ,  Gerard Lebesherais

    发明人： Gerard Boudon ,  Pierre Mollier ,  Gerard Lebesherais

    IPC分类号： H04L25/38 ,  H04L25/45 ,  H04L25/48 ,  H04L25/49 ,  H04J3/06 ,  H04L3/00 ,  H04L25/34

    CPC分类号： H04L25/45 ,  H04L25/49

    摘要： In the transmitting chip, the bits are serialized and applied to a coding circuit in which bit stream (D) and its complement (D) are transformed into two signals (PH1 and PH2) under the control of a saw-tooth clock signal CK'. Signals (PH1 and PH2) are sent to the receiving chip, wherein they are applied to a decoding circuit which generates two signals (DJ) and (DK) representative of the data bits and a recovered clock signal CLK. The three signals (DJ, DK and CLK) as well as a frame signal (F) are used by a converting and demultiplexing circuit for assembling bytes of parallel data bits.

    摘要翻译： 在发送芯片中，将这些比特序列化并应用于编码电路，其中，在锯齿时钟信号CK的控制下，比特流（D）及其补码（＆amp; upbar＆D）被变换成两个信号（PH1和PH2） '。 信号（PH1和PH2）被发送到接收芯片，其中它们被应用于产生表示数据位的两个信号（＆amp; upbar＆D）和（＆amp; upbar＆D）的解码电路和恢复的时钟信号CLK。 三个信号（＆upbar＆D，＆upbar＆D和CLK）以及帧信号（F）由转换和解复用电路用于组合并行数据位的字节。

    Decoding and selection circuit for a monolithic memory
    6.
    发明授权
    Decoding and selection circuit for a monolithic memory 失效
    单片存储器的解码和选择电路

    公开(公告)号：US4394752A

    公开(公告)日：1983-07-19

    申请号：US276136

    申请日：1981-06-22

    申请人： Gerard Boudon ,  Bernard Denis ,  Virginie de Grivel ,  Pierre Mollier

    发明人： Gerard Boudon ,  Bernard Denis ,  Virginie de Grivel ,  Pierre Mollier

    IPC分类号： G11C11/41 ,  G11C11/413 ,  G11C11/415 ,  G11C16/08 ,  G11C17/18 ,  G11C7/00

    CPC分类号： G11C17/18 ,  G11C11/415 ,  G11C16/08

    摘要： A word line selection circuit includes a conventional Schottky diode decoder and a driver transistor which is connected to a word line. A word line is selected when the transistor is conductive and all associated diodes of the decoder are off. The base current of the driver transistor is defined by a control transistor whose conductivity is opposite to that of the driver transistor and which applies the selection current to the base of the driver transistor. A regulating transistor forms a current mirror with the control transistor to regulate the selection current. A compensation circuit associated with the regulating transistor modulates the collector current of the regulating transistor as a function of the driver transistor factor.

    摘要翻译： 字线选择电路包括传统的肖特基二极管解码器和连接到字线的驱动晶体管。 当晶体管导通并且解码器的所有相关二极管关闭时，选择字线。 驱动晶体管的基极电流由与驱动晶体管的导通性相反的控制晶体管限定，并将选择电流施加到驱动晶体管的基极。 调节晶体管与控制晶体管形成电流镜以调节选择电流。 与调节晶体管相关联的补偿电路根据驱动晶体管因素调制调节晶体管的集电极电流。

    Logic circuits for forming VLSI logic networks
    7.
    发明授权
    Logic circuits for forming VLSI logic networks 失效
    用于形成VLSI逻辑网络的逻辑电路

    公开(公告)号：US4950927A

    公开(公告)日：1990-08-21

    申请号：US403062

    申请日：1989-09-05

    申请人： Gerard Boudon ,  Armand Brunin ,  Bernard Denis ,  Pierre Mollier ,  Philippe Stoppa

    发明人： Gerard Boudon ,  Armand Brunin ,  Bernard Denis ,  Pierre Mollier ,  Philippe Stoppa

    IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/06 ,  H03K19/003 ,  H03K19/082 ,  H03K19/084 ,  H03K19/088

    CPC分类号： H03K19/084 ,  H03K19/088

    摘要： A DTT type basic logic circuit exhibiting improved immunity to noise and including input diodes for receiving input signals A, B, . . .; an input transistor the emitter of which receives an additional input signal X and the base of which is connected to the anodes of the input diodes; and an output inverter transistor disposed so that the signal at the output thereof represents the logic function X(AB . . .). From this circuit, a family of logic circuits suitable for realizing very-large-scale-integration logic networks in a master slice can be developed. The master slice comprises general-purpose cells in which pre-diffused semiconductor elements can be interconnected to form the desired circuits.

    摘要翻译： 具有改进的抗噪声能力的DTT型基本逻辑电路，包括用于接收输入信号A，B的输入二极管。 。 。 输入晶体管，其发射极接收附加的输入信号X，其基极连接到输入二极管的阳极; 以及输出反相晶体管，其输出端的信号表示逻辑功能＆upbar＆X（AB ...）。 从该电路可以开发适合在主片中实现大规模集成逻辑网络的逻辑电路系列。 主切片包括通用单元，其中预扩散半导体元件可以互连以形成期望的电路。

    Duplicated circuit arrangement for fast transmission and repairability
    8.
    发明授权
    Duplicated circuit arrangement for fast transmission and repairability 失效
    重复电路布置，可快速传输和修复

    公开(公告)号：US4856000A

    公开(公告)日：1989-08-08

    申请号：US96569

    申请日：1987-09-08

    申请人： Michel Bauge ,  Gerard Boudon ,  Pierre Mollier ,  Jean-Luc Peter ,  Yiannis J. Yamour

    发明人： Michel Bauge ,  Gerard Boudon ,  Pierre Mollier ,  Jean-Luc Peter ,  Yiannis J. Yamour

    IPC分类号： G06F11/18 ,  G06F11/16

    CPC分类号： G06F11/16

    摘要： Duplicated circuit arrangement comprising a main processor (30) and its P bit data bus (44), and two identical redundant devices (21:22), each device is comprised of a processing element (23;35) performing the same task in parallel on a P bits word, and send/receive circuits (24,25;36,37) controlled by the main processor through lines (SR11 to SR22) to transmit said word to and from said main processor. For each device, the send/receive circuits are split into two parts. Send/receive circuit of the first device (21) is split in two parts (24, 25); the first part (24) handles the P/2 Most Significant Bits (MSB's) and the second part (25) handles the P/2 Less Significant Bits (LSB's). In normal operation, during the transmission step, only the first part (24) is allowed to send bits on one half (33) of the data bus (44). Symmetrically send/receive circuit of the second device (22), is also split in two parts (36, 37); the first section (36) handles the P/2 Most Significant bits (MSB's) and the second part (37) handles the P/2 Less Significant Bits Z(LSB's); only the second part (37) is allowed to send bits on the other half (34) of the data bus (44). Therefore, the data bus driving effort is equally shared between the two devices, the maximum number of simultaneous switching is P/2 for each device. This reduction allows greater transmission speed on large busses.

    SELF-SYNCHRONISING BIT ERROR ANALYSER AND CIRCUIT
    9.
    发明申请
    SELF-SYNCHRONISING BIT ERROR ANALYSER AND CIRCUIT 失效
    自同步位错误分析器和电路

    公开(公告)号：US20070011534A1

    公开(公告)日：2007-01-11

    申请号：US11164690

    申请日：2005-12-01

    申请人： Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

    发明人： Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3171

    摘要： A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

    摘要翻译： 一种自同步数据总线分析器，包括发生器LFSR，接收器LFSR和比较器，其中发生器LFSR产生通过数据总线传送到比较器的第一数据组; 并且其中所述比较器将所述第一数据集与由所述接收器LFSR生成的第二数据集进行比较，并且调整所述接收器LFSR，直到所述第二数据集与所述第一数据集基本相同。

    Self-synchronising bit error analyser and circuit
    10.
    发明授权
    Self-synchronising bit error analyser and circuit 失效
    自同步位误差分析器和电路

    公开(公告)号：US07404115B2

    公开(公告)日：2008-07-22

    申请号：US11164690

    申请日：2005-12-01

    申请人： Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

    发明人： Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3171

    摘要： A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

    摘要翻译： 一种自同步数据总线分析器，包括发生器LFSR，接收器LFSR和比较器，其中发生器LFSR产生通过数据总线传送到比较器的第一数据组; 并且其中所述比较器将所述第一数据集与由所述接收器LFSR生成的第二数据集进行比较，并且调整所述接收器LFSR，直到所述第二数据集与所述第一数据集基本相同。