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61 条记录 (耗时 0.02 秒)

    Structure and method for topography free SOI integration
    31.
    发明授权
    Structure and method for topography free SOI integration 有权
    地形自由SOI集成的结构和方法

    公开(公告)号：US08936996B2

    公开(公告)日：2015-01-20

    申请号：US12958429

    申请日：2010-12-02

    申请人： Ravi M. Todi ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

    发明人： Ravi M. Todi ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L21/76 ,  H01L29/02 ,  H01L21/762

    CPC分类号： H01L29/02 ,  H01L21/76254

    摘要： A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.

    摘要翻译： 提供了包括具有特征的半导体氧化物层的半导体结构。 具有特征的半导体氧化物层位于有源半导体层和手柄基板之间。 半导体结构包括有源半导体层的平坦化顶表面，使得半导体氧化物层位于平坦化的顶表面之下。 半导体氧化物层内的特征与有源半导体层的表面配合。

    Lateral epitaxial grown SOI in deep trench structures and methods of manufacture
    32.
    发明授权
    Lateral epitaxial grown SOI in deep trench structures and methods of manufacture 有权
    深沟槽结构中的横向外延生长SOI和制造方法

    公开(公告)号：US08692307B2

    公开(公告)日：2014-04-08

    申请号：US13530519

    申请日：2012-06-22

    申请人： Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

    发明人： Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

    IPC分类号： H01L27/108

    CPC分类号： H01L28/60 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

    摘要： Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer comprising a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI.

    摘要翻译： 公开了深沟槽电容器结构和制造方法。 该方法包括在包括衬底，掩埋氧化物层（BOX）和硅（SOI））膜的晶片中形成深沟槽结构。 该结构包括晶片，其包括衬底，掩埋绝缘体层和在整个层中具有单晶结构的绝缘体上硅层（SOI）层。 该结构还包括基板中的第一板和与第一板直接接触的绝缘体层。 掺杂多晶硅与绝缘体层直接接触，并且与SOI的单晶结构直接接触。

    SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY
    33.
    发明申请
    SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY 有权
    使用固体相外延片的子图形宽度FINFET

    公开(公告)号：US20140061793A1

    公开(公告)日：2014-03-06

    申请号：US13597752

    申请日：2012-08-29

    申请人： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

    发明人： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/12 ,  H01L29/06 ,  H01L21/336

    CPC分类号： H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

    摘要： A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

    摘要翻译： 介电心轴结构形成在单晶半导体层上。 非晶半导体材料层沉积在单晶半导体层的物理暴露表面和心轴结构的表面上。 可选地，非晶半导体材料层可以注入至少一种不同的半导体材料。 在采用单晶半导体层作为种子层的非晶半导体材料层上进行固相外延，从而形成厚度均匀的外延半导体材料层。 外延半导体材料层的剩余部分是单晶半导体鳍片，并且这些鳍片的厚度是亚光刻的。 在去除介电心轴结构之后，可以采用单晶半导体鳍形成半导体器件。

    Field effect transistors with low body resistance and self-balanced body potential
    35.
    发明授权
    Field effect transistors with low body resistance and self-balanced body potential 有权
    具有低体电阻和自平衡体电位的场效应晶体管

    公开(公告)号：US08564069B1

    公开(公告)日：2013-10-22

    申请号：US13590212

    申请日：2012-08-21

    申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/088

    CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/027 ,  H01L29/0615 ,  H01L29/78

    摘要： Embodiments of the invention relate generally to semiconductor devices and, more particularly, to semiconductor devices having field effect transistors (FETs) with a low body resistance and, in some embodiments, a self-balanced body potential where multiple transistors share same body potential. In one embodiment, the invention includes a field effect transistor (FET) comprising a source within a substrate, a drain within the substrate, and an active gate atop the substrate and between the source and the drain, an inactive gate structure atop the substrate and adjacent the source or the drain, a body adjacent the inactive gate, and a discharge path within the substrate for releasing a charge from the FET, the discharge path lying between the active gate of the FET and the body, wherein the discharge path is substantially perpendicular to a width of the active gate.

    摘要翻译： 本发明的实施例大体上涉及半导体器件，更具体地，涉及具有低体电阻的场效应晶体管（FET）的半导体器件，在一些实施例中，具有多个晶体管共享相同体电位的自平衡体电位。 在一个实施例中，本发明包括场效应晶体管（FET），其包括在衬底内的源极，衬底内的漏极，以及位于衬底顶部和源极与漏极之间的有源栅极，在衬底顶部的非活性栅极结构， 邻近源极或漏极，与非活性栅极相邻的主体以及衬底内的用于从FET释放电荷的放电路径，放电路径位于FET的有源栅极和主体之间，其中放电路径基本上 垂直于有源栅极的宽度。

    Recessed Single Crystalline Source and Drain For Semiconductor-On-Insulator Devices
    36.
    发明申请
    Recessed Single Crystalline Source and Drain For Semiconductor-On-Insulator Devices 有权
    嵌入式半导体绝缘体器件的单晶硅和漏极

    公开(公告)号：US20130105898A1

    公开(公告)日：2013-05-02

    申请号：US13285162

    申请日：2011-10-31

    申请人： Geng Wang ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

    发明人： Geng Wang ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66477 ,  H01L21/84 ,  H01L27/1203

    摘要： After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer.

    摘要翻译： 在形成栅极叠层之后，要形成源极和漏极的区域通过顶部半导体层凹陷，并进入绝缘体上半导体（SOI）的掩埋的单晶稀土氧化物层的上部， 衬底，从而形成源极沟槽和漏极沟槽。 在源极沟槽和漏极沟槽的每一个中分别形成外延对齐于埋入的单晶稀土氧化物层的嵌入式单晶半导体部分，以分别形成凹陷源和凹陷漏极。 可以将栅极电介质的底表面之上的凹陷源和凹陷漏极的突起最小化，以减少与栅极电极的寄生电容耦合，同时通过凹陷源和凹陷漏极的增加的厚度提供低的源极电阻和漏极电阻，相对于 顶部半导体层的厚度。

    Structure and method to fabricate pFETS with superior GIDL by localizing workfunction
    37.
    发明授权
    Structure and method to fabricate pFETS with superior GIDL by localizing workfunction 失效
    通过定位功能来制造具有优异GIDL的pFETS的结构和方法

    公开(公告)号：US08299530B2

    公开(公告)日：2012-10-30

    申请号：US12717375

    申请日：2010-03-04

    申请人： Chengwen Pei ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

    发明人： Chengwen Pei ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/12 ,  H01L21/8238

    CPC分类号： H01L21/22 ,  H01L21/8238 ,  H01L27/092

    摘要： A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.

    摘要翻译： 提供了一种半导体结构及其形成方法，其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏，使得pFET的栅极/ SD（源极/漏极）重叠区域为 适应平带，但不影响设备通道区域的功能。 该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。 所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。 沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。 该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域，其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。 通过离子注入或退火可形成局部功能调谐区域。

    Lateral epitaxial grown SOI in deep trench structures and methods of manufacture
    39.
    发明授权
    Lateral epitaxial grown SOI in deep trench structures and methods of manufacture 有权
    深沟槽结构中的横向外延生长SOI和制造方法

    公开(公告)号：US08232163B2

    公开(公告)日：2012-07-31

    申请号：US12916864

    申请日：2010-11-01

    申请人： Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

    发明人： Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/60 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

    摘要： Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall of the deep trench structure in the substrate by an implant process. The implant processes contaminate exposed edges of the SOI film in the deep trench structure. The method further includes removing the contaminated exposed edges of the SOI film by an etching process to form a void in the SOI film. The method further includes growing epitaxial Si in the void, prior to completing a capacitor structure.

    摘要翻译： 公开了深沟槽电容器结构和制造方法。 该方法包括在包括衬底，掩埋氧化物层（BOX）和硅（SOI））膜的晶片中形成深沟槽结构。 该方法还包括通过植入工艺在衬底中的深沟槽结构的侧壁上形成板。 植入工艺污染了深沟槽结构中SOI膜的暴露边缘。 该方法还包括通过蚀刻工艺去除SOI膜的污染的暴露边缘，以在SOI膜中形成空隙。 该方法还包括在完成电容器结构之前在空隙中生长外延Si。