Selective storage of data in levels of a cache memory
    31.
    发明申请
    Selective storage of data in levels of a cache memory 失效
    在高速缓冲存储器的级别中选择性地存储数据

    公开(公告)号:US20080059707A1

    公开(公告)日:2008-03-06

    申请号:US11513554

    申请日:2006-08-31

    CPC classification number: G06F12/0897 G06F12/128

    Abstract: In one embodiment, the present invention includes a method for incrementing a counter value associated with a cache line if the cache line is inserted into a first level cache, and storing the cache line into a second level cache coupled to the first level cache or a third level cache coupled to the second level cache based on the counter value, after eviction from the first level cache. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中,本发明包括一种用于在高速缓存行插入到第一级高速缓存中时递增与高速缓存线相关联的计数器值的方法,并且将高速缓存行存储到耦合到第一级高速缓存的第二级高速缓存或 在从第一级高速缓存驱逐之后,基于计数器值耦合到第二级高速缓存的第三级缓存。 描述和要求保护其他实施例。

    Providing quality of service (QoS) for cache architectures using priority information
    32.
    发明申请
    Providing quality of service (QoS) for cache architectures using priority information 有权
    使用优先级信息为缓存架构提供服务质量(QoS)

    公开(公告)号:US20080040554A1

    公开(公告)日:2008-02-14

    申请号:US11503633

    申请日:2006-08-14

    CPC classification number: G06F12/126

    Abstract: In one embodiment, the present invention includes a method for associating a first priority indicator with first data stored in a first entry of a cache memory to indicate a priority level of the first data, and updating a count value associated with the first priority indicator. The count value may then be used in determining an appropriate cache line for eviction. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中,本发明包括一种用于将第一优先级指示符与存储在高速缓冲存储器的第一条目中的第一数据相关联以指示第一数据的优先级,以及更新与第一优先级指示符相关联的计数值的方法。 然后可以将计数值用于确定用于驱逐的适当的高速缓存行。 描述和要求保护其他实施例。

    Scheduling workloads based on cache asymmetry
    38.
    发明授权
    Scheduling workloads based on cache asymmetry 有权
    基于缓存不对称调度工作负载

    公开(公告)号:US08898390B2

    公开(公告)日:2014-11-25

    申请号:US13042547

    申请日:2011-03-08

    CPC classification number: G06F12/0842 G06F9/46 G06F9/4881 G06F2209/483

    Abstract: In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads.

    Abstract translation: 在一个实施例中,处理器包括第一高速缓存和第二高速缓存,与第一高速缓存相关联的第一核和与第二高速缓存相关联的第二核。 高速缓存具有非对称尺寸,并且调度器可以至少部分地基于对至少一个线程的训练阶段期间获得的不对称性和结果高速缓存性能信息的认识来智能地将线程调度到核心。

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