公开(公告)号：US20030016836A1

公开(公告)日：2003-01-23

申请号：US10147436

申请日：2002-05-15

Applicant: STMicroelectronics Limited

Inventor： Tahir Rashid

IPC: H04B015/00

CPC classification number: H03G3/345 ,  H03G3/34

Abstract: A mute switch including a field effect transistor receiving a mute control signal at its gate for selectively supplying an audio signal from an input node to an output node. A bipolar transistor is connected between the input node and the FET for reducing the voltage level of the audio signal prior to its application to the input node, and a further bipolar transistor is connected between the FET and the output node for raising the voltage level of the audio signal prior to its application to the output node. This serves to maintain the DC bias level of the audio output signal independently of the status of the mute control signal.

Abstract translation: 一种静音开关，包括场效应晶体管，在其栅极处接收静音控制信号，用于选择性地将音频信号从输入节点提供给输出节点。 双极晶体管连接在输入节点和FET之间，用于在施加到输入节点之前降低音频信号的电压电平，并且在FET和输出节点之间连接另外的双极晶体管，以提高电压电平 该音频信号在其应用于输出节点之前。 这用于独立于静音控制信号的状态来维持音频输出信号的DC偏置电平。

公开(公告)号：US20030011592A1

公开(公告)日：2003-01-16

申请号：US10133971

申请日：2002-04-26

Applicant: STMicroelectronics Limited

Inventor： Trefor Southwell ,  Magne Sandven

IPC: G06T017/00

CPC classification number: G06T15/005

Abstract: A graphic processor having an index processing unit for pre-processing a list of vertices making up a three-dimensional image. The method of pre-processing comprising the following steps. First, decomposing the three-dimensional image into a plurality of primitive elements each defined by a set of vertices, each vertex comprising vertex information stored in a vertex storage area and addressable by a vertex index. Then receiving said vertex indices and creating a set of unique indices identifying a batch of vertices and loading only the vertices corresponding to said unique indices into the vertex storage area. Finally creating transformed primitive elements from transformed vertex information addressed in the vertex storage area using the unique indices.

Abstract translation: 一种具有索引处理单元的图形处理器，用于预处理构成三维图像的顶点列表。 预处理方法包括以下步骤。 首先，将三维图像分解为由一组顶点定义的多个基元，每个顶点包含存储在顶点存储区域中并且可由顶点索引寻址的顶点信息。 然后接收所述顶点索引并创建一组唯一索引，其识别一批顶点，并仅将与所述唯一索引对应的顶点加载到顶点存储区域中。 最后使用独特的索引从顶点存储区域中寻址的变换顶点信息创建变换的原始元素。

公开(公告)号：US20020171459A1

公开(公告)日：2002-11-21

申请号：US10104994

申请日：2002-03-22

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: H03K021/00

CPC classification number: H03K23/68 ,  H03K23/546

Abstract: A digital frequency divider includes phase control of the output signal in increments of whole or half cycles of the input frequency. Whole cycle phase control is achieved by varying (logically or physically) the tap off point of a shift register loaded with a bit pattern for appropriate division. Half cycle phase changes are achieved by a multiplexer selecting one of two signals every half cycle.

Abstract translation: 数字分频器包括以输入频率的整个或半个周期为增量的输出信号的相位控制。 通过改变（逻辑上或物理上）通过加载位模式的移位寄存器的抽头点进行适当划分来实现整个周期相位控制。 半周期相位变化通过多路复用器每半周期选择两个信号之一来实现。

公开(公告)号：US20020131298A1

公开(公告)日：2002-09-19

申请号：US10085987

申请日：2002-02-27

Applicant: STMicroelectronics Limited

Inventor： William Bryan Barnes

IPC: G11C011/34

CPC classification number: H03K5/249 ,  G11C7/065 ,  H03K3/356139 ,  H03K5/1534 ,  H03K19/0963

Abstract: To establish whether a precharged node remains isolated or alternatively is subject to discharge, the conventional circuit allows uncertainty. For a period after evaluation starts, the conventional circuit will give a tentative result that may subsequently turn out to be wrong. During evaluation power is dissipated. A differential offset dynamic comparator and timing circuit are used to evaluate whether the node is being discharged. Because the comparator has an offset, much smaller deviations from the precharge potential can be sensed: because it is dynamic, it does not consume steady state current. The timing circuit permits precise knowledge of when to look at the output: before the timing period has elapsed, the result is known to be invalid.

Abstract translation: 为了确定预充电节点是否保持隔离或者可替代地进行放电，常规电路允许不确定性。 在评估开始一段时间后，常规电路将给出一个可能随后证明是错误的初步结果。 评估过程中耗电。 差分偏移动态比较器和定时电路用于评估节点是否正在放电。 由于比较器具有偏移，因此可以感测到与预充电电位相差较小的偏差：因为它是动态的，所以它不消耗稳态电流。 定时电路可以准确了解何时查看输出：在定时周期过去之前，已知结果无效。

公开(公告)号：US20040233911A1

公开(公告)日：2004-11-25

申请号：US10794581

申请日：2004-03-05

Applicant: STMICROELECTRONICS LIMITED

Inventor： Matt Morris

IPC: H04L012/28

CPC classification number: H04J3/0632 ,  H04J3/0685

Abstract: A stream processing system is described in which packets of an input stream each include individual timestamps which represent relative delays between the packets. A programmable counter generates continuously count values that are compared with the timestamps in the packet stream. An output controller determines whether or not to release packets from an output port based on the result of the comparison, preferably only releasing packets when the programmable count value equals the timestamp.

Abstract translation: 描述了流处理系统，其中输入流的分组各自包括表示分组之间的相对延迟的各个时间戳。 可编程计数器产生与分组流中的时间戳相比较的连续计数值。 输出控制器基于比较的结果来确定是否从输出端口释放分组，优选地仅当可编程计数值等于时间戳时才释放分组。

公开(公告)号：US20040228342A1

公开(公告)日：2004-11-18

申请号：US10779466

申请日：2004-02-16

Applicant: STMicroelectronics Limited

Inventor： Matt Morris

IPC: H04L012/56

CPC classification number: H04L49/25 ,  H04L49/103

Abstract: The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination ports. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher bit rate output stream. An assignment data structure identifies for each input stream the or each destination to which it is to be routed, and a packet allocation data structure holds information about the packets and information about the destination of the packets to allow a memory holding the packets to be controlled accordingly.

Abstract translation: 讨论数据流的路由，特别是将一个或多个输入流路由到一个或多个输出目的地端口。 讨论合并输入流的能力，使得几个低比特率输入分组流可以被合并到更高比特率的输出流中。 分配数据结构为每个输入流标识其要路由的每个目的地，并且分组分配数据结构保存关于分组的信息和关于分组的目的地的信息，以允许控制分组的存储器 相应地。

公开(公告)号：US20040119618A1

公开(公告)日：2004-06-24

申请号：US10632564

申请日：2003-08-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.I.

Inventor： Philip Mattos ,  Marco Losi

IPC: H03M009/00

CPC classification number: H03H17/0664 ,  G01S19/30

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a separate acquisition engine is used which includes a sample reducer for combining samples of a received signal for correlation with a locally generated version of a GPS code. A serial to parallel converter converts the reduced samples to parallel words which are correlated in parallel with locally generated words of the GPS code.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，使用单独的采集引擎，其包括用于组合接收信号的采样以与本地生成的GPS码版本进行相关的采样减速器。 串行到并行转换器将缩减的样本转换成与GPS码的本地生成的字并行相关的并行字。

公开(公告)号：US20040119528A1

公开(公告)日：2004-06-24

申请号：US10620834

申请日：2003-07-15

Applicant: STMicroelectronics Limited

Inventor： Tahir Rashid

IPC: G05F003/02

CPC classification number: G05F3/225 ,  G05F3/30

Abstract: The described embodiments of the invention relate to a voltage reference generator which can be produced using new process technologies and which is still compatible with older designs/products. This is achieved by the introduction of circuitry to generate an offset voltage independently of the main reference voltage generation circuitry.

Abstract translation: 所描述的本发明的实施例涉及一种可以使用新的工艺技术制造的并且与旧的设计/产品兼容的电压参考发生器。 这通过引入电路来实现，以产生独立于主参考电压产生电路的偏移电压。

公开(公告)号：US20030185067A1

公开(公告)日：2003-10-02

申请号：US10354908

申请日：2003-01-30

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: G11C007/00

CPC classification number: G06F13/28

Abstract: A semiconductor integrated circuit for use in direct memory access (DMA) has two sources which communicate with a bus through a bus interface. A DMA access signal generator is coupled to the bus interface and asserts a DMA access output signal at a DMA access signal pin whenever either of the sources requires a DMA access. The need for separate DMA access signal pins for each of the two sources is thereby avoided. With targets on two separate integrated circuits, a single DMA access pin can be used for the two targets, while chip select signals at chip select pins on the source integrated circuit indicate which of the two targets is intended for the DMA access.

Abstract translation: 用于直接存储器访问（DMA）的半导体集成电路具有通过总线接口与总线通信的两个源。 DMA访问信号发生器耦合到总线接口，并且每当任何一个源需要DMA访问时，在DMA访问信号引脚处断言DMA访问输出信号。 因此避免了对于两个源中的每一个的单独的DMA访问信号引脚的需要。 通过两个独立的集成电路上的目标，两个目标可以使用单个DMA访问引脚，而源集成电路芯片选择引脚上的芯片选择信号指示两个目标中的哪一个用于DMA访问。

公开(公告)号：US20030177483A1

公开(公告)日：2003-09-18

申请号：US10099455

申请日：2002-03-14

Applicant: STMicroelectronics Limited

Inventor： Trefor Southwell ,  Peter Hedinger

IPC: G06F009/44

CPC classification number: G06F12/126 ,  G06F8/54

Abstract: A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses which man onto a set of cache locations and introducing into the executable program gaps at other sets of memory addresses which map onto the same set of cache locations.

Abstract translation: 一种链接多个对象文件以生成可执行程序的方法，所述方法包括在执行程序时在目标文件中识别要被锁定到高速缓存中的至少一个例程，将所述例程定位在一组存储器地址 到一组缓存位置，并将映射到同一组高速缓存位置的其他存储器地址集合引入可执行程序间隙。