公开(公告)号：US08169039B2

公开(公告)日：2012-05-01

申请号：US12848565

申请日：2010-08-02

Applicant: Takaaki Negoro

Inventor： Takaaki Negoro

IPC: H01L27/12 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L29/42384 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78624

Abstract: A disclosed semiconductor device includes an MOS transistor having an N-type low-concentration drain region, a source region, an ohmic drain region, a P-type channel region, an ohmic channel region, a gate isolation film, and a gate electrode. The N-type low-concentration drain region includes two low-concentration drain layers in which the N-type impurity concentration of the upper layer is higher than that of the lower layer; the P-type channel region includes two channel layers in which the P-type impurity concentration of the upper layer is lower than that of the lower layer; and the gate electrode is formed on the P-type channel region and the N-type low-concentration drain region and disposed to be separated from the ohmic drain region when viewed from the top.

Abstract translation: 所公开的半导体器件包括具有N型低浓度漏极区域，源极区域，欧姆漏极区域，P型沟道区域，欧姆沟道区域，栅极隔离膜和栅极电极的MOS晶体管。 N型低浓度漏极区域包括两个低浓度漏极层，其中上层的N型杂质浓度高于下层的N型杂质浓度; P型沟道区域包括上层的P型杂质浓度低于下层的P沟道层的两个沟道层; 并且栅极电极形成在P型沟道区域和N型低浓度漏极区域上，并且从顶部观察时被设置为与欧姆漏极区域分离。

公开(公告)号：US20120032733A1

公开(公告)日：2012-02-09

申请号：US13196983

申请日：2011-08-03

Applicant: Takaaki NEGORO

Inventor： Takaaki NEGORO

IPC: G05F3/02

CPC classification number: H01L27/0883 ,  G06F1/28 ,  G06F1/30 ,  H01L27/092 ,  H01L27/1203

Abstract: A semiconductor integrated circuit device includes a power-supply terminal to which a power-supply voltage is input; and multiple MOS transistors including an Nch deplete mode MOS transistor functioning as a current source and at least one Pch enhancement mode MOS transistor formed on a silicon-on-insulator substrate including a silicon substrate, a buried-oxide film, and a silicon activate layer, each of the multiple MOS transistors dimensioned so that a bottom of a source diffusion layer and a bottom of a drain diffusion layer reach the buried-oxide film, the at least one Pch enhancement mode MOS transistor being connected to the supply terminal through the Nch depletion mode MOS transistor. The Nch depletion mode MOS transistor has electrical characteristics such that a source voltage thereof is higher than a silicon substrate voltage thereof and a saturation current of the Nch depletion mode MOS transistor is decreased.

Abstract translation: 半导体集成电路装置包括输入电源电压的电源端子; 以及多个MOS晶体管，其包括用作电流源的Nch耗尽型MOS晶体管和形成在包括硅衬底，掩埋氧化膜和硅激活层的绝缘体上硅衬底上的至少一个Pch增强模式MOS晶体管 所述多个MOS晶体管的每一个尺寸使得源极扩散层的底部和漏极扩散层的底部到达掩埋氧化物膜，所述至少一个Pch增强模式MOS晶体管通过Nch连接到所述电源端子 耗尽型MOS晶体管。 N沟道耗尽型MOS晶体管具有使得其源极电压高于其硅衬底电压的电特性，并且Nch耗尽型MOS晶体管的饱和电流降低。

公开(公告)号：US20110042745A1

公开(公告)日：2011-02-24

申请号：US12848565

申请日：2010-08-02

Applicant: Takaaki NEGORO

Inventor： Takaaki NEGORO

IPC: H01L27/12 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L29/42384 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78624

Abstract: A disclosed semiconductor device includes an MOS transistor having an N-type low-concentration drain region, a source region, an ohmic drain region, a P-type channel region, an ohmic channel region, a gate isolation film, and a gate electrode. The N-type low-concentration drain region includes two low-concentration drain layers in which the N-type impurity concentration of the upper layer is higher than that of the lower layer; the P-type channel region includes two channel layers in which the P-type impurity concentration of the upper layer is lower than that of the lower layer; and the gate electrode is formed on the P-type channel region and the N-type low-concentration drain region and disposed to be separated from the ohmic drain region when viewed from the top.

Abstract translation: 所公开的半导体器件包括具有N型低浓度漏极区域，源极区域，欧姆漏极区域，P型沟道区域，欧姆沟道区域，栅极隔离膜和栅极电极的MOS晶体管。 N型低浓度漏极区域包括两个低浓度漏极层，其中上层的N型杂质浓度高于下层的N型杂质浓度; P型沟道区域包括上层的P型杂质浓度低于下层的P沟道层的两个沟道层; 并且栅极电极形成在P型沟道区域和N型低浓度漏极区域上，并且从顶部观察时被设置为与欧姆漏极区域分离。

公开(公告)号：US20090033420A1

公开(公告)日：2009-02-05

申请号：US12144852

申请日：2008-06-24

Applicant: Takaaki Negoro

Inventor： Takaaki Negoro

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F3/345 ,  H03F2203/45636

Abstract: A disclosed operational amplifier circuit with a multi-stage amplifier configuration provides fast-response and high withstand-voltage characteristics without using high withstand-voltage transistors as output transistors in its amplifying stages. The output voltage range of a differential amplifier circuit in a first stage is limited by voltage clamping based on a reverse withstand voltage of a bipolar diode. The output voltage range of an amplifier circuit in a second stage is limited by voltage clamping based on a reverse withstand voltage of another bipolar diode. A constant voltage circuit and an apparatus including such an operational amplifier circuit are also disclosed.

Abstract translation: 具有多级放大器配置的公开的运算放大器电路提供快速响应和高耐压特性，而不需要在其放大级中使用高耐压晶体管作为输出晶体管。 第一级差分放大器电路的输出电压范围受到基于双极型二极管的反向耐受电压的钳位限制。 第二级放大器电路的输出电压范围受到基于另一双极二极管的反向耐受电压的钳位限制。 还公开了一种恒压电路和包括这种运算放大器电路的装置。

公开(公告)号：US06979864B2

公开(公告)日：2005-12-27

申请号：US11115340

申请日：2005-04-27

Applicant: Takaaki Negoro ,  Keiji Fujimoto

Inventor： Takaaki Negoro ,  Keiji Fujimoto

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/732 ,  H01L29/735 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7816 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7801 ,  H01L29/7835

Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d. Since the source 11s, well region 23, and drain region 24 are respectively self-aligned to the gate electrode 11g, resultant transistor characteristics are stabilized, and the decrease in the on resistance and improved drain threshold voltages can be achieved. Also disclosed herein are bipolar transistors with LDMOS structures, which are capable of obviating the breakdown of gate dielectric layers even at high applied voltage and achieving improved stability in transistor characteristics.

公开(公告)号：US20050194639A1

公开(公告)日：2005-09-08

申请号：US11115340

申请日：2005-04-27

Applicant: Takaaki Negoro ,  Keiji Fujimoto

Inventor： Takaaki Negoro ,  Keiji Fujimoto

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/732 ,  H01L29/735 ,  H01L29/78 ,  H01L31/113

CPC classification number: H01L29/7816 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7801 ,  H01L29/7835

Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d. Since the source 11s, well region 23, and drain region 24 are respectively self-aligned to the gate electrode 11g, resultant transistor characteristics are stabilized, and the decrease in the on resistance and improved drain threshold voltages can be achieved. Also disclosed herein are bipolar transistors with LDMOS structures, which are capable of obviating the breakdown of gate dielectric layers even at high applied voltage and achieving improved stability in transistor characteristics.

Abstract translation: 公开了具有LDMOS结构的LDMOS晶体管和双极晶体管，用于在高耐压设备应用中的适用。 LDMOS晶体管包括形成在P型衬底1中的漏极阱区21，并且在空间上分离的漏极阱区21是杂质浓度大于漏极区21的杂质浓度的沟道阱区23和中等浓度漏极区24 ，其通过热处理同时形成具有大的扩散深度。 源极11s形成在沟道阱区23中，而漏极11d形成在漏极区24中，杂质浓度大于漏极区24的杂质浓度。 此外，在阱区上形成栅电极11g，覆盖部分重叠的部分与阱区23和漏区24并与漏11d分离。 由于源极11s，阱区23和漏极区24分别与栅极11g自对准，所以晶体管的特性得到稳定，并且可以实现导通电阻的降低和漏极阈值电压的改善。 本文还公开了具有LDMOS结构的双极型晶体管，其即使在高施加电压下也能够消除栅极电介质层的击穿，并且实现晶体管特性的改善的稳定性。

公开(公告)号：US10078010B2

公开(公告)日：2018-09-18

申请号：US14978172

申请日：2015-12-22

Applicant: Katsuhiko Aisu ,  Hirofumi Watanabe ,  Takaaki Negoro ,  Yoshinori Ueda ,  Yasukazu Nakatani ,  Kazuhiro Yoneda ,  Katsuyuki Sakurano

Inventor： Katsuhiko Aisu ,  Hirofumi Watanabe ,  Takaaki Negoro ,  Yoshinori Ueda ,  Yasukazu Nakatani ,  Kazuhiro Yoneda ,  Katsuyuki Sakurano

IPC: G01J1/44 ,  H04N5/361 ,  H04N5/365 ,  H04N5/378

CPC classification number: G01J1/44 ,  G01J2001/444 ,  G01J2001/4473 ,  H04N5/361 ,  H04N5/3655 ,  H04N5/378

Abstract: A photoelectric conversion device includes a pixel cell including a phototransistor, a reference cell including a reference transistor having a temperature characteristic identical to that of the phototransistor and having a fixed electrical state, an analog-to-digital converter that converts an analog output of the pixel cell into a digital output, a correction amount computation unit that computes a correction amount for the digital output of the analog-to-digital converter based on an output of the reference cell and a reference value, and a correction unit that corrects the digital output of the analog-to-digital converter based on the correction amount.

公开(公告)号：US09923019B2

公开(公告)日：2018-03-20

申请号：US14935973

申请日：2015-11-09

Applicant: Takaaki Negoro ,  Yoshinori Ueda ,  Katsuyuki Sakurano ,  Yasukazu Nakatani ,  Kazuhiro Yoneda ,  Katsuhiko Aisu

Inventor： Takaaki Negoro ,  Yoshinori Ueda ,  Katsuyuki Sakurano ,  Yasukazu Nakatani ,  Kazuhiro Yoneda ,  Katsuhiko Aisu

IPC: H01L31/0224 ,  H04N5/378 ,  H04N5/361 ,  H01L31/0352 ,  H01L31/18 ,  H01L27/146

CPC classification number: H01L27/14681 ,  H01L27/14612

Abstract: A semiconductor device for converting incident light into an electric current includes a semiconductor substrate; an electrode embedded in the semiconductor substrate; an insulation film contacting the electrode in the semiconductor substrate; a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and a third semiconductor region of the first conductivity type, formed sequentially in a depth direction from a side of a front face of the semiconductor substrate; and a fourth semiconductor region of the second conductivity type contacting the insulation film and the second semiconductor region. An impurity concentration of the fourth semiconductor region is greater than an impurity concentration of the second semiconductor region.

公开(公告)号：US09571770B2

公开(公告)日：2017-02-14

申请号：US13745197

申请日：2013-01-18

Applicant: Yutaka Hayashi ,  Toshitaka Ota ,  Yasushi Nagamune ,  Hirofumi Watanabe ,  Kazuhiro Yoneda ,  Katsuhiko Aisu ,  Takaaki Negoro

Inventor： Yutaka Hayashi ,  Toshitaka Ota ,  Yasushi Nagamune ,  Hirofumi Watanabe ,  Kazuhiro Yoneda ,  Katsuhiko Aisu ,  Takaaki Negoro

IPC: H04N5/378 ,  H01L27/144

CPC classification number: H04N5/378 ,  H01L27/144

Abstract: A sense circuit includes a differential amplifier circuit including an inverting input section, a non-inverting input section and an output section, an electrical capacitor connected between the inverting input section and the output section, and a field effect transistor including a source, a drain, and a gate. One of the source and the drain is connected to the inverting input section, and the other of the source and the drain is connected to the output section. A reference potential is supplied to the non-inverting input section, and an output section of a photoelectric conversion cell having an added switching function is connected to the inverting input section.

Abstract translation: 感测电路包括差分放大器电路，其包括反相输入部分，非反相输入部分和输出部分，连接在反相输入部分和输出部分之间的电容器，以及场效应晶体管，其包括源极，漏极 ，和一个门。 源极和漏极之一连接到反相输入部分，源极和漏极中的另一个连接到输出部分。 参考电位被提供给非反相输入部分，并且具有增加的开关功能的光电转换单元的输出部分连接到反相输入部分。

公开(公告)号：US09362328B2

公开(公告)日：2016-06-07

申请号：US13793445

申请日：2013-03-11

Applicant: Takaaki Negoro ,  Hirofumi Watanabe ,  Yutaka Hayashi ,  Toshitaka Ota ,  Yasushi Nagamune

Inventor： Takaaki Negoro ,  Hirofumi Watanabe ,  Yutaka Hayashi ,  Toshitaka Ota ,  Yasushi Nagamune

IPC: H01L27/146 ,  H01L29/73 ,  H01L31/11 ,  H01L29/739

CPC classification number: H01L27/14681 ,  H01L27/14683 ,  H01L29/73 ,  H01L29/739 ,  H01L31/1105

Abstract: The invention relates to a semiconductor device having a vertical transistor bipolar structure of emitter, base, and collector formed in this order from a semiconductor substrate surface in a depth direction. The semiconductor device includes an electrode embedded from the semiconductor substrate surface into the inside and insulated by an oxide film. In the surface of the substrate, a first-conductivity-type first semiconductor region, a second-conductivity-type second semiconductor region, and a first-conductivity-type third semiconductor region are arranged, from the surface side, inside a semiconductor device region surrounded by the electrode and along the electrode with the oxide film interposed therebetween, the second semiconductor region located below the first semiconductor region, the third semiconductor region located below the second semiconductor region. The electrode is insulated from the first to third semiconductor regions, and current gain is variable through application of voltage to the electrode.

Abstract translation: 本发明涉及一种半导体器件，其具有从半导体衬底表面沿深度方向依次形成的发射极，基极和集电极的垂直晶体管双极结构。 半导体器件包括从半导体衬底表面嵌入内部并由氧化物膜绝缘的电极。 在基板的表面中，从第一导电型第一半导体区域，第二导电型第二半导体区域和第一导电型第三半导体区域的表面侧配置在半导体器件区域 被电极围绕并且沿着电极，氧化膜插入其间，位于第一半导体区域下方的第二半导体区域，位于第二半导体区域下方的第三半导体区域。 电极与第一至第三半导体区域绝缘​​，电流增益可通过向电极施加电压而变化。