公开(公告)号：US20060264034A1

公开(公告)日：2006-11-23

申请号：US11415115

申请日：2006-05-02

申请人： Koichi Endo ,  Yasuto Sumi ,  Katsuyuki Adachi

发明人： Koichi Endo ,  Yasuto Sumi ,  Katsuyuki Adachi

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/4824 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a plurality of semiconductor elements; and a first wire and a second wire provided to connect the semiconductor elements in parallel. The first wire and the second wire include respective wires formed in multiple wiring layers. Each wiring layer includes the first wire and the second wire formed alternately and in parallel. The wires are formed as to intersect each other in adjacent wiring layers. The first wires are connected with each other through a via-connection at an intersection of the first wires and the second wires are connected with each other through a via-connection at an intersection of the second wires.

摘要翻译： 半导体器件包括多个半导体元件; 以及设置成并联连接半导体元件的第一线和第二线。 第一线和第二线包括形成在多个布线层中的各个线。 每个布线层包括交替且平行地形成的第一线和第二线。 导线形成为在相邻布线层中彼此相交。 第一配线通过第一配线的交叉点处的通路连接而彼此连接，并且第二配线通过第二配线的交叉点处的通孔连接而彼此连接。

公开(公告)号：US20130093003A1

公开(公告)日：2013-04-18

申请号：US13607255

申请日：2012-09-07

申请人： Hiroyuki IRIFUNE ,  Wataru SAITO ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Hiroshi OHTA ,  Junji SUZUKI

发明人： Hiroyuki IRIFUNE ,  Wataru SAITO ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Hiroshi OHTA ,  Junji SUZUKI

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7811

摘要： A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third. diffusion layers are the same.

摘要翻译： 半导体器件包括各自具有多个扩散层的第一，第二和第三半导体层。 第一扩散层的第一方向宽度相同。 第一扩散层内的杂质量从第一半导体层的底端向顶端逐渐增加。 第二扩散层的第一方向宽度相同。 第二扩散层内的杂质量相同。 第三扩散层的第一方向宽度比第一扩散层的第一方向宽度和第二扩散层的第一方向宽度在相同水平处窄，并且从第一扩散层的第一方向宽度逐渐变窄到 第三半导体层。 第三者内的杂质量。 扩散层是相同的。

公开(公告)号：US08227854B2

公开(公告)日：2012-07-24

申请号：US11936412

申请日：2007-11-07

申请人： Syotaro Ono ,  Wataru Saito ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

发明人： Syotaro Ono ,  Wataru Saito ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

IPC分类号： H01L29/66

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095

摘要： A semiconductor device includes: a drift layer having a superjunction structure; a semiconductor base layer selectively formed in a part of one surface of the drift layer; a first RESURF layer formed around a region having the semiconductor base layer formed thereon; a second semiconductor RESURF layer of a conductivity type which is opposite to a conductivity type of the first semiconductor RESURF layer; a first main electrode connected to a first surface of the drift layer; and a second main electrode connected to a second surface of the drift layer. The first RESURF layer is connected to the semiconductor base layer. The second semiconductor RESURF layer is in contact with the first semiconductor RESURF layer.

摘要翻译： 一种半导体器件包括：具有超结构结构的漂移层; 选择性地形成在所述漂移层的一个表面的一部分中的半导体基层; 在其上形成有半导体基底层的区域周围形成的第一RESURF层; 与第一半导体RESURF层的导电类型相反的导电类型的第二半导体RESURF层; 连接到所述漂移层的第一表面的第一主电极; 以及连接到漂移层的第二表面的第二主电极。 第一RESURF层连接到半导体基层。 第二半导体RESURF层与第一半导体RESURF层接触。

公开(公告)号：US08013360B2

公开(公告)日：2011-09-06

申请号：US12764763

申请日：2010-04-21

申请人： Wataru Saito ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Wataru Sekine

发明人： Wataru Saito ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Wataru Sekine

IPC分类号： H01L29/66

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7722 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/8611

摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.

摘要翻译： 半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及 第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。 高电阻半导体层的掺杂浓度低于第一半导体柱区域。 边界区域设置在设备中心区域和边缘终端部分之间。 边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

公开(公告)号：US20100200936A1

公开(公告)日：2010-08-12

申请号：US12764763

申请日：2010-04-21

申请人： Wataru SAITO ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Wataru Sekine

发明人： Wataru SAITO ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Wataru Sekine

IPC分类号： H01L29/78

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7722 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/8611

摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.

摘要翻译： 半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及 第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。 高电阻半导体层的掺杂浓度低于第一半导体柱区域。 边界区域设置在设备中心区域和边缘终端部分之间。 边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

公开(公告)号：US07759732B2

公开(公告)日：2010-07-20

申请号：US11680912

申请日：2007-03-01

申请人： Wataru Saito ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

发明人： Wataru Saito ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

IPC分类号： H01L27/088 ,  H01L23/62

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.

摘要翻译： 功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和形成在第一半导体层上的第二导电类型的第三半导体层，并且沿着平行于第一半导体层的表面的至少一个方向交替布置; 第一主电极; 选择性地形成在第二半导体层的表面和第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地形成在第四半导体层的表面中的第一导电类型的第五半导体层; 第二主电极; 和控制电极。 第二和第三半导体层中的至少一个具有沿着一个方向的掺杂剂浓度分布，掺杂剂浓度分布在其两端以外的位置处具有局部最小值。

公开(公告)号：US07605426B2

公开(公告)日：2009-10-20

申请号：US11933869

申请日：2007-11-01

申请人： Wataru Saito ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

发明人： Wataru Saito ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： A power semiconductor device includes: a semiconductor substrate; a gate insulating film; a control electrode insulated from the semiconductor substrate by the gate insulating film; a first main electrode provided on a lower surface side of the semiconductor substrate; and a second main electrode provided on an upper surface side of the semiconductor substrate. The semiconductor substrate includes: a first first-conductivity-type semiconductor layer with its lower surface connected to the first main electrode; a second first-conductivity-type semiconductor layer and a third second-conductivity-type semiconductor layer formed on the first first-conductivity-type semiconductor layer and alternately arranged parallel to the upper surface of the semiconductor substrate; a trench formed in a directly overlying region of the third second-conductivity-type semiconductor layer, with part of the second main electrode buried in the trench; a fourth second-conductivity-type semiconductor layer selectively formed in a surface of the second first-conductivity-type semiconductor layer and connected to the second main electrode; a fifth first-conductivity-type semiconductor layer selectively formed in a surface of the fourth second-conductivity-type semiconductor layer and connected to the second main electrode; and a sixth second-conductivity-type semiconductor layer formed at a bottom of the trench and connected to the second main electrode. Impurity concentration in the sixth second-conductivity-type semiconductor layer is higher than impurity concentration in the fourth second-conductivity-type semiconductor layer, and lower surface of the sixth second-conductivity-type semiconductor layer is located below lower surface of the fourth second-conductivity-type semiconductor layer.

摘要翻译： 功率半导体器件包括：半导体衬底; 栅极绝缘膜; 通过栅极绝缘膜与半导体衬底绝缘的控制电极; 设置在所述半导体基板的下表面侧的第一主电极; 以及设置在半导体衬底的上表面侧的第二主电极。 半导体衬底包括：第一第一导电型半导体层，其下表面连接到第一主电极; 形成在第一第一导电型半导体层上的第二第一导电型半导体层和第三第二导电型半导体层，并且交替地平行于半导体基板的上表面布置; 形成在所述第三第二导电型半导体层的直接覆盖区域中的沟槽，其中所述第二主电极的一部分埋在所述沟槽中; 选择性地形成在所述第二第一导电型半导体层的表面并连接到所述第二主电极的第四第二导电型半导体层; 第五第一导电型半导体层，选择性地形成在所述第四第二导电型半导体层的表面上，并连接到所述第二主电极; 以及形成在所述沟槽的底部并连接到所述第二主电极的第六第二导电型半导体层。 第六第二导电型半导体层中的杂质浓度高于第四第二导电型半导体层中的杂质浓度，第六第二导电型半导体层的下表面位于第四第二导电型半导体层的下表面下方 导电型半导体层。

公开(公告)号：US20090101974A1

公开(公告)日：2009-04-23

申请号：US12252872

申请日：2008-10-16

申请人： Wataru SAITO ,  Syotaro Ono ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Nana Hatano

发明人： Wataru SAITO ,  Syotaro Ono ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Nana Hatano

IPC分类号： H01L29/78

CPC分类号： H01L29/0634 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7811

摘要： A semiconductor device includes an n+ type semiconductor substrate 1 and a super junction region that has, on the top of the substrate 1, an n and p type pillar regions 2 and 3 provided alternately. The device also includes, in the top surface of the super junction region, a p type base region 4 and an n type source layer 5. The device also includes a gate electrode 7 on the region 4 and layer 5 via a gate-insulating film 6, a drain electrode 9 on the bottom of the substrate 1, and a source electrode 8 on the top of the substrate 1. In the top surface of the super junction region in the terminal region, a RESURF region 10 is formed. The RESURF region has a comb-like planar shape with repeatedly-formed teeth having tips facing the end portion of the terminal region.

摘要翻译： 半导体器件包括n +型半导体衬底1和超结区，其在衬底1的顶部上交替设置n和p型柱状区域2,3。 该器件还在超结区域的顶表面中包括ap型基极区域4和n型源极层5.该器件还包括位于区域4上的栅电极7和通过栅极绝缘膜6的层5 ，基板1底部的漏电极9以及基板1顶部的源极8.在端子区域的超结区域的上表面形成有RESURF区域10。 RESURF区域具有梳状平面形状，具有重复形成的齿，其尖端面向终端区域的端部。

公开(公告)号：US20060197192A1

公开(公告)日：2006-09-07

申请号：US11181926

申请日：2005-07-15

申请人： Yasuto Sumi ,  Koichi Endo

发明人： Yasuto Sumi ,  Koichi Endo

IPC分类号： H01L31/075

CPC分类号： H01L29/0692 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/0619 ,  H01L29/8611

摘要： A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type provided on the semiconductor layer, the first semiconductor region being one of an anode region and a cathode region; a second semiconductor region of the first conductivity type provided on the first semiconductor region, the second semiconductor region being the other of the anode region and the cathode region; and a semiconductor buried region of the second conductivity type provided between the semiconductor layer and the first semiconductor region. The semiconductor buried region has an aperture where the first semiconductor region is in contact with the semiconductor layer.

摘要翻译： 半导体器件包括：第一导电类型的半导体层; 设置在所述半导体层上的第二导电类型的第一半导体区域，所述第一半导体区域是阳极区域和阴极区域之一; 设置在第一半导体区域上的第一导电类型的第二半导体区域，第二半导体区域是阳极区域和阴极区域中的另一个; 以及设置在所述半导体层和所述第一半导体区域之间的所述第二导电类型的半导体掩埋区域。 半导体掩埋区域具有第一半导体区域与半导体层接触的孔径。