公开(公告)号：US20090257292A1

公开(公告)日：2009-10-15

申请号：US12292897

申请日：2008-11-28

Applicant: Kwang Jin Lee ,  Du Eung Kim ,  Yong Jun Lee

Inventor： Kwang Jin Lee ,  Du Eung Kim ,  Yong Jun Lee

IPC: G11C7/22

CPC classification number: G11C13/0061 ,  G11C7/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/004

Abstract: One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.

Abstract translation: 一个实施例包括非易失性存储单元阵列和被配置为在非易失性存储单元阵列中写入数据之后的一段时间内禁止非易失性存储单元阵列的读操作的读单元。

公开(公告)号：US20090168494A1

公开(公告)日：2009-07-02

申请号：US12318241

申请日：2008-12-23

Applicant: Yong-Jun Lee ,  Kwang-Jin Lee ,  Taek-Sung Kim ,  Kwang-Ho Kim ,  Woo-Yeong Cho ,  Hyun-Ho Choi ,  Hye Jin Kim

Inventor： Yong-Jun Lee ,  Kwang-Jin Lee ,  Taek-Sung Kim ,  Kwang-Ho Kim ,  Woo-Yeong Cho ,  Hyun-Ho Choi ,  Hye Jin Kim

IPC: G11C11/00 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0078 ,  G11C2213/72

Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.

Abstract translation: 在一个实施例中，半导体器件包括非易失性存储单元阵列，被配置为写入非易失性存储单元阵列的写入电路和控制电路。 控制电路被配置为存储至少一个擦除指示符。 擦除指示符与非易失性存储单元阵列的至少一部分相关联并且指示逻辑状态。 控制电路被配置为在非易失性存储单元阵列的相关部分的擦除操作期间，控制写入电路将由擦除指示符指示的逻辑状态写入非易失性存储单元阵列。

公开(公告)号：US20130087165A1

公开(公告)日：2013-04-11

申请号：US13635641

申请日：2010-10-28

Applicant: Yong Jun Lee ,  Jeen Gee Kim

Inventor： Yong Jun Lee ,  Jeen Gee Kim

IPC: A45D33/00

CPC classification number: A45D33/003 ,  A45C13/008 ,  A45C13/1084 ,  A45D33/00 ,  A45D33/006 ,  A45D40/0068 ,  A45D40/222 ,  A45D2200/051 ,  Y10S206/823

Abstract: The present invention can magnify a sealing characteristic and prevent deformation of hard rubber by coupling a container body with a rib formed on an external cap and through double-injection molding by an elastomer having a different elastic restoring force from the hard rubber charged and hardened in an injection concave groove of a support body that accommodates an internal container, in order to maximize product reliability by improving a sealing structure of a make-up base container or a cosmetic container and providing a clear air-tight effect since the sealing structure cannot be transformed even in case of long-term use. Further, the invention provides regular and firm adhesion without the unequal distribution of the coupling intensity between internal sealing members when the external cap is closed, such that superior sealing performance is accomplished even in case of long-term use and an aesthetic point on the appearance is increased since an opening and closing means is not necessary, and further, it is possible to solve the unstable storage state which is caused when the opening and closing means is equipped.

Abstract translation: 本发明可以放大密封特性，并且通过将容器主体与形成在外盖上的肋结合在一起，并且通过具有不同弹性恢复力的弹性体通过双重注射成型从硬化橡胶充填和固化而放大密封特性并防止硬橡胶的变形 容纳内部容器的支撑体的注入凹槽，以便通过改善补充基座容器或化妆品容器的密封结构来提高产品的可靠性，并提供透明的气密效果，因为密封结构不能 即使长期使用也会发生变化。 此外，本发明提供了规则和牢固的粘附，而在外盖闭合时内密封件之间的耦合强度分布不均匀，从而即使在长期使用的情况下也能实现出色的密封性能，并且外观上的美观点 由于不需要打开和关闭装置，所以增加，并且还可以解决装备开闭装置时引起的不稳定的储存状态。

公开(公告)号：US08293612B2

公开(公告)日：2012-10-23

申请号：US12494028

申请日：2009-06-29

Applicant: Yong Jun Lee

Inventor： Yong Jun Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66659

Abstract: A method for manufacturing a lateral double diffused metal oxide semiconductor (LDMOS) device includes forming an oxide layer on a semiconductor substrate, forming first and second trenches by partially etching the oxide layer and the semiconductor substrate, forming a small trench overlapping with the second trench so that the second trench has a stepped structure, and depositing one or more dielectric layers so that the first trench forms a device isolation layer defining a semiconductor device region and the second trench having a stepped structure forms a drain extension device isolation layer. The breakdown voltage of the LDMOS device may be improved while reducing the on-resistance, thereby improving the operational reliability of the device.

Abstract translation: 制造横向双重扩散金属氧化物半导体（LDMOS）器件的方法包括在半导体衬底上形成氧化物层，通过部分蚀刻氧化物层和半导体衬底形成第一和第二沟槽，形成与第二沟槽重叠的小沟槽 使得第二沟槽具有阶梯结构，并且沉积一个或多个电介质层，使得第一沟槽形成限定半导体器件区域的器件隔离层，并且具有阶梯结构的第二沟槽形成漏极延伸器件隔离层。 可以在降低导通电阻的同时提高LDMOS器件的击穿电压，从而提高器件的工作可靠性。

公开(公告)号：US20110222330A1

公开(公告)日：2011-09-15

申请号：US13032848

申请日：2011-02-23

Applicant: Yong-Jun LEE ,  Kwang Jin LEE ,  Joon Min PARK ,  Huik Won SEO

Inventor： Yong-Jun LEE ,  Kwang Jin LEE ,  Joon Min PARK ,  Huik Won SEO

IPC: G11C17/00 ,  G11C11/00

CPC classification number: G11C17/18 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0059 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state.

Abstract translation: 非易失性存储器件包括一次性可编程（OTP）锁定位寄存器。 非易失性存储器件包括可变电阻存储单元阵列，其包括存储数据的OTP块和存储指示数据是否可更改的OTP锁定状态信息的寄存器。 寄存器包括可变存储单元。 OTP锁定状态信息的初始值被设置为程序保护状态。

公开(公告)号：US20100164065A1

公开(公告)日：2010-07-01

申请号：US12648910

申请日：2009-12-29

Applicant: Yong-Jun Lee

Inventor： Yong-Jun Lee

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L21/0273 ,  H01L21/32139 ,  H01L28/60

Abstract: A capacitor of a semiconductor device and a method for manufacturing the same includes a lower metal layer on and/or over a semiconductor substrate; an insulating layer formed on and/or over the lower metal layer with step difference; and an upper electrode on and/or over the insulating layer pattern, wherein a top corner of the upper electrode is rounded so that a curvature pattern is formed on the top corner of the upper electrode.

Abstract translation: 半导体器件的电容器及其制造方法包括在半导体衬底上和/或之上的下金属层; 在步进差异的下金属层上和/或上方形成绝缘层; 以及在绝缘层图案之上和/或之上的上电极，其中上电极的顶角是圆形的，使得在上电极的顶角上形成曲率图案。

公开(公告)号：US20100123195A1

公开(公告)日：2010-05-20

申请号：US12615096

申请日：2009-11-09

Applicant: Yong-Jun Lee

Inventor： Yong-Jun Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66681

Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device and a method of manufacturing the same. A LDMOS device may include a high voltage well formed over a substrate, a reduced surface field region formed thereover which may be adjacent a body region, and/or an isolation layer. An isolation layer may include a predetermined area formed over a reduced surface field region, may be partially overlapped with a top surface of a substrate and/or may include an area formed adjacent a high voltage well. A low voltage well may be formed over a substrate. A gate electrode may extend from a predetermined top surface of a body region to a predetermined top surface of an isolation layer. A drain region may be formed over a low voltage well. A source region may be formed over a body region and may have at least a portion formed under a gate electrode.

Abstract translation: 横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法。 LDMOS器件可以包括在衬底上形成的高电压井，形成在其上的减小的表面场区域，其可以与身体区域相邻，和/或隔离层。 隔离层可以包括在还原表面场区域上形成的预定区域，可以与衬底的顶表面部分地重叠，和/或可以包括邻近高电压阱形成的区域。 可以在衬底上形成低电压阱。 栅电极可以从体区的预定顶表面延伸到隔离层的预定顶表面。 可以在低电压阱上形成漏极区。 源极区域可以形成在体区域上并且可以具有形成在栅电极下方的至少一部分。

公开(公告)号：US20100006937A1

公开(公告)日：2010-01-14

申请号：US12494028

申请日：2009-06-29

Applicant: Yong Jun Lee

Inventor： Yong Jun Lee

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762

CPC classification number: H01L29/7835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66659

Abstract: A method for manufacturing a lateral double diffused metal oxide semiconductor (LDMOS) device includes forming an oxide layer on a semiconductor substrate, forming first and second trenches by partially etching the oxide layer and the semiconductor substrate, forming a small trench overlapping with the second trench so that the second trench has a stepped structure, and depositing one or more dielectric layers so that the first trench forms a device isolation layer defining a semiconductor device region and the second trench having a stepped structure forms a drain extension device isolation layer. The breakdown voltage of the LDMOS device may be improved while reducing the on-resistance, thereby improving the operational reliability of the device.

Abstract translation: 制造横向双重扩散金属氧化物半导体（LDMOS）器件的方法包括在半导体衬底上形成氧化物层，通过部分蚀刻氧化物层和半导体衬底形成第一和第二沟槽，形成与第二沟槽重叠的小沟槽 使得第二沟槽具有阶梯结构，并且沉积一个或多个电介质层，使得第一沟槽形成限定半导体器件区域的器件隔离层，并且具有阶梯结构的第二沟槽形成漏极延伸器件隔离层。 可以在降低导通电阻的同时提高LDMOS器件的击穿电压，从而提高器件的工作可靠性。

公开(公告)号：US07560332B2

公开(公告)日：2009-07-14

申请号：US11733711

申请日：2007-04-10

Applicant: Kyoung-Woo Lee ,  Wan-Jae Park ,  Jeong-Hoon Ahn ,  Kyung-Tae Lee ,  Mu-Kyeng Jung ,  Yong-Jun Lee ,  Il-Goo Kim ,  Soo-Geun Lee

Inventor： Kyoung-Woo Lee ,  Wan-Jae Park ,  Jeong-Hoon Ahn ,  Kyung-Tae Lee ,  Mu-Kyeng Jung ,  Yong-Jun Lee ,  Il-Goo Kim ,  Soo-Geun Lee

IPC: H01L21/8234

CPC classification number: H01L28/40 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract translation: 本发明的实施例包括具有高电容的MIM电容器，其可以在没有影响现有技术的问题的情况下被制造。 这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。 可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。 将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

公开(公告)号：US5904633A

公开(公告)日：1999-05-18

申请号：US774639

申请日：1996-12-30

Applicant: Yong-Jun Lee

Inventor： Yong-Jun Lee

IPC: F16H37/02 ,  F16H37/08

CPC classification number: F16H37/021

Abstract: The continuously variable transmission (CVT) includes an input shaft delivering power from an engine, an output shaft having a first drive member, and a secondary shaft having a first driven member operationally connected with the first drive member. The CVT further includes a pulley member transferring power from the input shaft to the secondary shaft. The pulley member includes a drive pulley and a driven pulley operationally connected to the drive pulley. The pulley member forms a first power pathway for communicating the engine power from the input shaft to the output shaft via the secondary shaft. The CVT also includes a power by-pass member for selectively supplying power from the input shaft directly to the output shaft to form a second power pathway for communicating the engine power from the input shaft directly to the output shaft which by-passes the first power pathway.

Abstract translation: 无级变速器（CVT）包括从发动机输出功率的输入轴，具有第一驱动构件的输出轴和具有与第一驱动构件可操作地连接的第一从动构件的副轴。 CVT还包括将动力从输入轴传递到副轴的滑轮构件。 滑轮构件包括驱动滑轮和从动皮带轮，该从动皮带轮可操作地连接到驱动皮带轮。 滑轮构件形成用于经由副轴将来自输入轴的发动机功率传递到输出轴的第一动力通路。 CVT还包括功率旁路构件，用于从输入轴直接向输出轴选择性地供电，以形成第二动力通道，用于将来自输入轴的发动机功率直接传递到输出轴，该输出轴绕过第一功率 途径。