公开(公告)号：US20090135347A1

公开(公告)日：2009-05-28

申请号：US12184842

申请日：2008-08-01

Applicant: Woo-Seok Jeon ,  Jang-Soo Kim ,  Young-Wook Lee ,  Jung-In Park ,  Hi-Kuk Lee ,  Shi-Yul Kim ,  Jin-Seuk Kim ,  Jae-Hyoung Youn ,  Ki-Won Kim ,  Su-Hyoung Kang

Inventor： Woo-Seok Jeon ,  Jang-Soo Kim ,  Young-Wook Lee ,  Jung-In Park ,  Hi-Kuk Lee ,  Shi-Yul Kim ,  Jin-Seuk Kim ,  Jae-Hyoung Youn ,  Ki-Won Kim ,  Su-Hyoung Kang

IPC: G02F1/1335 ,  G03F7/20 ,  B05D5/06

CPC classification number: G02F1/13439 ,  G02F1/133514

Abstract: A manufacturing method of a display device, wherein the manufacturing method for an embodiment includes: forming color filters in a plurality of pixel regions; forming a conductive layer on the color filters; and separating the conductive layer in each of the pixel regions through a photolithography process and forming a pixel electrode; wherein a groove is formed between the adjacent color filters having different colors at boundaries between the pixel regions; and wherein the photolithography process uses a negative photoresist material.

Abstract translation: 一种显示装置的制造方法，其中，实施例的制造方法包括：在多个像素区域中形成滤色器; 在滤色片上形成导电层; 以及通过光刻工艺分离每个像素区域中的导电层并形成像素电极; 其中在所述像素区域之间的边界处在相邻的具有不同颜色的滤色器之间形成凹槽; 并且其中所述光刻工艺使用负性光致抗蚀剂材料。

公开(公告)号：US20090033820A1

公开(公告)日：2009-02-05

申请号：US12152619

申请日：2008-05-14

Applicant: Woo-Geun Lee ,  Shi-Yul Kim ,  Jae-Hyoung Youn ,  Young-Wook Lee

Inventor： Woo-Geun Lee ,  Shi-Yul Kim ,  Jae-Hyoung Youn ,  Young-Wook Lee

IPC: G02F1/1343 ,  G02F1/133

CPC classification number: G02F1/136286 ,  G02F1/136209 ,  G02F2001/13606 ,  G02F2001/136218 ,  G02F2001/136222 ,  G02F2201/40

Abstract: A liquid crystal display to prevent light leakage with an improvement of aperture ratio and a reduction of load of a data line is provided. The liquid crystal display includes a gate line and a storage electrode line formed on a insulating substrate and apart from each other, a first data line and a second data line intersecting the gate line, a first pixel electrode defined by the gate line and the first data line, and a second pixel electrode defined by the gate line and the second data line and neighboring the first pixel electrode. Also, a blocking electrode between the first pixel electrode and the second pixel electrode is included, wherein at least portion of the first data line is disposed under the first pixel electrode, and at least portion of the blocking electrode is disposed under the second pixel electrode and apart from the first data line.

Abstract translation: 提供了一种液晶显示器，用于防止光泄漏，同时提高了开口率和减少了数据线的负载。 液晶显示器包括形成在绝缘基板上并且彼此分开的栅极线和存储电极线，与栅极线相交的第一数据线和第二数据线，由栅极线和第一栅极线限定的第一像素电极 数据线和由栅极线和第二数据线限定并与第一像素电极相邻的第二像素电极。 此外，包括第一像素电极和第二像素电极之间的阻挡电极，其中第一数据线的至少一部分设置在第一像素电极下方，并且阻挡电极的至少一部分设置在第二像素电极下方 并且除了第一条数据线之外。

公开(公告)号：US20080237037A1

公开(公告)日：2008-10-02

申请号：US12035086

申请日：2008-02-21

Applicant: Chong-Chul CHAI ,  Mee-Hye Jung ,  Woo-Geun Lee ,  Woo-Seok Jeon ,  Young-Wook Lee ,  Jung-In Park ,  Jun-Hyung Souk ,  Won-Kie Chang ,  Shi-Yul Kim

Inventor： Chong-Chul CHAI ,  Mee-Hye Jung ,  Woo-Geun Lee ,  Woo-Seok Jeon ,  Young-Wook Lee ,  Jung-In Park ,  Jun-Hyung Souk ,  Won-Kie Chang ,  Shi-Yul Kim

IPC: G03F9/00

CPC classification number: G03F1/36 ,  G03F1/00 ,  G03F1/50

Abstract: A mask includes a transparent substrate, a light-blocking layer and a halftone layer. The light-blocking layer includes a source electrode pattern portion including a first electrode portion, a second electrode portion and a third electrode portion, and a drain electrode pattern portion disposed between the second electrode portion and the third electrode portion. The halftone layer includes a halftone portion corresponding to a spaced-apart portion between the source electrode pattern portion and the drain electrode pattern portion, and a dummy halftone portion more protrusive than ends of the second electrode portion and the third electrode portion. Thus, a photoresist pattern corresponding to a channel portion of a thin film transistor (TFT) may be formed with a uniform thickness, to thereby prevent an excessive etching of the channel portion.

Abstract translation: 掩模包括透明基板，遮光层和半色调层。 遮光层包括包括第一电极部分，第二电极部分和第三电极部分的源电极图案部分和设置在第二电极部分和第三电极部分之间的漏电极图案部分。 半色调层包括对应于源电极图案部分和漏电极图案部分之间的间隔部分的半色调部分和比第二电极部分和第三电极部分的端部更突出的虚拟半色调部分。 因此，可以形成对应于薄膜晶体管（TFT）的沟道部分的光致抗蚀剂图案，其厚度均匀，从而防止通道部分的过度蚀刻。

公开(公告)号：US20080111933A1

公开(公告)日：2008-05-15

申请号：US11868865

申请日：2007-10-08

Applicant: Young-wook LEE ,  Woo-geun Lee ,  Kyung-sook Jeon ,  Youn-hee Cha ,  Jong-in Kim

Inventor： Young-wook LEE ,  Woo-geun Lee ,  Kyung-sook Jeon ,  Youn-hee Cha ,  Jong-in Kim

IPC: G02F1/1343

CPC classification number: G02F1/136286 ,  G02F1/13306 ,  H01L27/124 ,  H01L29/41733

Abstract: A display device includes a gate line delivering a gate on/off voltage, a data line insulated to the gate line, a pixel transistor including a gate electrode connected to the gate line, a drain electrode connected to the data line and a source electrode spaced apart with the drain electrode, a pixel electrode connected to the source electrode, a dummy gate line delivering a kick-back compensation voltage complimentary to the gate on/off voltage, and a compensation capacitance formed between a dummy gate electrode connected to the dummy gate line and a dummy source electrode connected to the pixel electrode.

Abstract translation: 显示装置包括栅极导通/截止电压的栅极线，与栅极线绝缘的数据线，像素晶体管，包括连接到栅极线的栅电极，连接到数据线的漏电极和间隔开的源电极 除了漏极之外，连接到源电极的像素电极，提供与栅极导通/截止电压互补的反冲补偿电压的虚拟栅极线以及连接到虚拟栅极的虚拟栅电极之间形成的补偿电容 线和连接到像素电极的虚拟源电极。

公开(公告)号：US20080080534A1

公开(公告)日：2008-04-03

申请号：US11857837

申请日：2007-09-19

Applicant: Kwang II LEE ,  Dong Hwan PARK ,  Jun Hee PARK ,  Chae Kyu KIM ,  Kyeong Deok MOON ,  Yong Seok JEONG ,  Young Wook LEE ,  Duck Ki AHN

Inventor： Kwang II LEE ,  Dong Hwan PARK ,  Jun Hee PARK ,  Chae Kyu KIM ,  Kyeong Deok MOON ,  Yong Seok JEONG ,  Young Wook LEE ,  Duck Ki AHN

IPC: H04L12/56

CPC classification number: H04L12/4625 ,  H04L12/2832 ,  H04L47/10 ,  H04L47/2491 ,  H04L47/70 ,  H04L47/786 ,  H04L47/805

Abstract: A bridge for heterogeneous QoS networks is provided. The bridge comprises an UPnP QoS processing unit, a bridge function unit and at least two of network drive drivers. The UPnP QoS processing unit collects connection information connected through the networks and QoS requirement information thereof through an UPnP QoS structure. The bridge function unit establishes and releases connection by allocating resources based on the collected connection information and QoS requirement information, and performs a bridging operation according to connection information of a received frame. At least two of network device drivers are physically connected to the networks.

Abstract translation: 提供了用于异构QoS网络的桥梁。 桥接器包括UPnP QoS处理单元，桥接功能单元和至少两个网络驱动器驱动器。 UPnP QoS处理单元通过UPnP QoS结构收集通过网络连接的连接信息及其QoS要求信息。 桥功能单元通过基于所收集的连接信息和QoS要求信息分配资源来建立和释放连接，并根据接收到的帧的连接信息执行桥接操作。 至少两个网络设备驱动程序物理连接到网络。

公开(公告)号：US20080073718A1

公开(公告)日：2008-03-27

申请号：US11861113

申请日：2007-09-25

Applicant: Young-Wook LEE ,  Woo-Geun Lee ,  Jung-In Park ,  Youn-Hee Cha

Inventor： Young-Wook LEE ,  Woo-Geun Lee ,  Jung-In Park ,  Youn-Hee Cha

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L29/41733 ,  H01L27/124 ,  H01L27/1288

Abstract: A mask that is capable of forming a thin-film transistor (TFT) with improved electrical characteristics is presented. The mask includes a drain mask pattern, a source mask pattern and a light-adjusting pattern. The drain mask pattern blocks light for forming a drain electrode. The source mask pattern blocks light for forming a source electrode and faces the drain mask pattern. A distance between the drain and source mask patterns is no more than the resolution of an exposing device. The light-adjusting pattern is formed between end portions of the source mask pattern and the drain mask pattern to block at least some light from entering a space between the source and drain mask patterns.

Abstract translation: 提出了能够形成具有改善的电特性的薄膜晶体管（TFT）的掩模。 掩模包括漏极掩模图案，源掩模图案和调光图案。 漏极掩模图案阻挡用于形成漏电极的光。 源极掩模图案阻挡用于形成源极的光并面向漏极掩模图案。 漏极和源极掩模图案之间的距离不大于曝光装置的分辨率。 光源调制图案形成在源掩模图案和漏极掩模图案的端部之间，以阻挡至少一些光进入源极和漏极掩模图案之间的空间。

公开(公告)号：US20070139572A1

公开(公告)日：2007-06-21

申请号：US11609144

申请日：2006-12-11

Applicant: Young-Wook LEE

Inventor： Young-Wook LEE

IPC: G02F1/136

CPC classification number: G02F1/134309 ,  G02F2001/134381 ,  G02F2201/128

Abstract: A thin film transistor array panel includes a substrate, a gate line disposed on the substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line contacting the semiconductor layer, a drain electrode contacting the semiconductor layer and separated from the data line, a pixel electrode disposed on the gate insulating layer and contacting the drain electrode, a passivation layer disposed on the pixel electrode, and a common electrode disposed on the passivation layer and including a unit electrode overlapping the pixel electrode.

Abstract translation: 薄膜晶体管阵列面板包括基板，设置在基板上的栅极线，设置在栅极线上的栅极绝缘层，设置在栅极绝缘层上的半导体层，与半导体层接触的数据线，接触的漏极电极 半导体层并与数据线分离，设置在栅极绝缘层上并接触漏电极的像素电极，设置在像素电极上的钝化层和设置在钝化层上的公共电极，并且包括与 像素电极。

公开(公告)号：US20070102770A1

公开(公告)日：2007-05-10

申请号：US11619451

申请日：2007-01-03

Applicant: Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

Inventor： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC: H01L29/76

CPC classification number: H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

Abstract: A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

Abstract translation: 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

公开(公告)号：US20060231957A1

公开(公告)日：2006-10-19

申请号：US11403292

申请日：2006-04-13

Applicant: Sung-Jin Kim ,  Young-Wook Lee ,  Keun-Kyu Song ,  Mun-Pyo Hong

Inventor： Sung-Jin Kim ,  Young-Wook Lee ,  Keun-Kyu Song ,  Mun-Pyo Hong

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00

CPC classification number: H01L29/78696 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/127 ,  H01L29/42392

Abstract: A transistor includes a wire formed on a substrate, the wire comprising a semiconductor core, a first cover enclosing a portion of the semiconductor core, and a second cover enclosing the first cover, a first electrode formed on the second cover of the wire, an insulating layer formed on the first electrode and having contact holes exposing portions the semiconductor core, and a second electrode and a third electrode connected to the wire through the contact holes.

Abstract translation: 晶体管包括形成在基板上的导线，所述导线包括半导体芯，封装半导体芯的一部分的第一盖和封闭第一盖的第二盖，形成在导线的第二盖上的第一电极， 绝缘层，其形成在所述第一电极上，并且具有暴露所述半导体芯的部分的接触孔，以及通过所述接触孔连接到所述电线的第二电极和第三电极。

公开(公告)号：US20050221546A1

公开(公告)日：2005-10-06

申请号：US11082967

申请日：2005-03-18

Applicant: Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

Inventor： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC: G02F1/1368 ,  G09F9/30 ,  G09G3/36 ,  G09G3/38 ,  H01L21/00 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

Abstract: A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

Abstract translation: 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。