公开(公告)号：US20220310500A1

公开(公告)日：2022-09-29

申请号：US17213006

申请日：2021-03-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Chih-Pin HUNG ,  Teck-Chong LEE ,  Chih-Yi HUANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065 ,  H01L21/48

Abstract: An assembly structure and a method for manufacturing an assembly structure are provided. The assembly structure includes a wiring structure and a semiconductor element. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the at least one dielectric layer, and defines an accommodating recess recessed from a top surface of the wiring structure. The wiring structure has a smooth surface extending from the top surface of the wiring structure to a surface of the accommodating recess. The semiconductor element is disposed in the accommodating recess.

公开(公告)号：US20210288024A1

公开(公告)日：2021-09-16

申请号：US17322764

申请日：2021-05-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Meng-Kai SHIH ,  Teck-Chong LEE ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US20210005761A1

公开(公告)日：2021-01-07

申请号：US16503318

申请日：2019-07-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Pin TSAI ,  Tsung-Yueh TSAI ,  Teck-Chong LEE

IPC: H01L31/02 ,  H01L25/16 ,  H01L31/0203

Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.

公开(公告)号：US20200335858A1

公开(公告)日：2020-10-22

申请号：US16388828

申请日：2019-04-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Sheng-Chi HSIEH ,  Chen-Chao WANG ,  Teck-Chong LEE

IPC: H01Q1/38 ,  H01L23/15 ,  H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L23/13 ,  H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01Q23/00

Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.

公开(公告)号：US20200118970A1

公开(公告)日：2020-04-16

申请号：US16158294

申请日：2018-10-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Teck-Chong LEE

IPC: H01L23/00 ,  H01L21/56

Abstract: A semiconductor package device includes a transparent carrier, a first patterned conductive layer, a second patterned conductive layer, and a first insulation layer. The transparent carrier has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface of the transparent carrier. The first patterned conductive layer has a first surface coplanar with the third surface of the transparent carrier. The second patterned conductive layer is disposed on the first surface of the transparent carrier and electrically isolated from the first patterned conductive layer. The first insulation layer is disposed on the transparent carrier and covers the first patterned conductive layer.

公开(公告)号：US20180138113A1

公开(公告)日：2018-05-17

申请号：US15352529

申请日：2016-11-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE ,  Yung-Shun CHANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H05K3/40 ,  H01L21/683

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2224/45099 ,  H01L2224/29099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device package includes a semiconductor chip, a glass substrate having a first surface facing the semiconductor chip and a second surface opposite to the first surface, the glass substrate defining a hole that traverses the glass substrate from the first surface to the second surface, an interconnect structure disposed in the hole, and a conductive bump disposed adjacent to the interconnect structure and protruded from the second surface, wherein the conductive bump and the interconnect structure include a same material.

公开(公告)号：US20170047276A1

公开(公告)日：2017-02-16

申请号：US14825326

申请日：2015-08-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE ,  Chi-Han CHEN ,  Sheng-Chi HSIEH

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/11

Abstract: The present disclosure relates to a semiconductor device package and a method for manufacturing the same. The semiconductor device package comprises a substrate, a first patterned conductive layer, an insulator layer, a second patterned conductive layer, and a dielectric layer. The first patterned conductive layer is disposed on a surface of the substrate. The insulator layer is disposed on the surface of the substrate and covers the first patterned conductive layer. The second patterned conductive layer is fully encapsulated by the insulator layer. The dielectric layer is disposed on the insulator layer.

Abstract translation: 本公开涉及一种半导体器件封装及其制造方法。 半导体器件封装包括衬底，第一图案化导电层，绝缘体层，第二图案化导电层和电介质层。 第一图案化导电层设置在基板的表面上。 绝缘体层设置在衬底的表面上并覆盖第一图案化导电层。 第二图案化导电层被绝缘体层完全封装。 电介质层设置在绝缘体层上。

公开(公告)号：US20170018550A1

公开(公告)日：2017-01-19

申请号：US14801730

申请日：2015-07-16

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Hsu-Chiang SHIH ,  Sheng-Chi HSIEH ,  Chien-Hua CHEN ,  Teck-Chong LEE

IPC: H01L27/08 ,  H01L23/48 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01G4/30 ,  H01L23/481 ,  H01L27/101 ,  H01L28/60 ,  H01L2224/18

Abstract: A semiconductor device and a method for manufacturing the same is described. The semiconductor device includes a substrate, a first capacitor and a second capacitor. The first capacitor includes a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer and has a first peripheral edge. The second conductive layer is disposed on the first insulating layer and has a second peripheral edge. The second capacitor includes a third conductive layer, a second insulating layer and the second conductive layer. The second insulating layer is disposed on the second conductive layer and has a third peripheral edge. The third conductive layer is disposed on the second insulating layer and has a fourth peripheral edge. The first, second, third and fourth peripheral edges are aligned with one another.

Abstract translation: 对半导体装置及其制造方法进行说明。 半导体器件包括衬底，第一电容器和第二电容器。 第一电容器包括第一导电层，第一绝缘层和第二导电层。 第一导电层设置在基板上。 第一绝缘层设置在第一导电层上并具有第一周边边缘。 第二导电层设置在第一绝缘层上并具有第二周边。 第二电容器包括第三导电层，第二绝缘层和第二导电层。 第二绝缘层设置在第二导电层上并具有第三外围边缘。 第三导电层设置在第二绝缘层上并具有第四周边。 第一，第二，第三和第四外围边缘彼此对准。