公开(公告)号：US20190127573A1

公开(公告)日：2019-05-02

申请号：US15801116

申请日：2017-11-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chean-Cheng SU ,  Chih-Pin HUNG ,  Shin-Luh TARNG ,  Chaung Chi WANG ,  Chao Ming TSENG ,  Shiu-Chih WANG

IPC: C08L67/04 ,  H01L21/673 ,  C08K5/00 ,  C08K5/09 ,  C08K3/36 ,  C08K3/04 ,  C08K5/5419

Abstract: A polylactic acid resin composition includes about 100 parts by weight of a polylactic acid resin, about 0.001 to about 3 parts by weight of a nucleating agent and about 3 to about 70 parts by weight of a filler. The polylactic acid resin composition can be processed into a biodegradable molded article or other product having a high impact strength and a high heat deflection temperature.

公开(公告)号：US20210074676A1

公开(公告)日：2021-03-11

申请号：US16563716

申请日：2019-09-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Meng-Kai SHIH ,  Teck-Chong LEE ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US20230411349A1

公开(公告)日：2023-12-21

申请号：US18239722

申请日：2023-08-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Meng-Kai SHIH ,  Teck-Chong LEE ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L24/33 ,  H01L24/17 ,  H01L24/73 ,  H01L23/5283 ,  H01L21/566 ,  H01L2224/02373 ,  H01L2224/73253 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2224/0231 ,  H01L2224/02381

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US20210327815A1

公开(公告)日：2021-10-21

申请号：US16850999

申请日：2020-04-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ian HU ,  Shin-Luh TARNG

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/50

Abstract: A substrate, a semiconductor package device and a method of manufacturing a semiconductor device package are provided. The substrate includes a low density wiring structure, a first middle density wiring structure and high density wiring structure. The first middle density wiring structure is electrically connected to the low density wiring structure. The high density wiring structure is electrically connected to the low density wiring structure. The high density wiring structure and the first middle density wiring structure are disposed side by side. A line space of a circuit layer of the low density wiring structure is greater than a line space of a circuit layer of the first middle density wiring structure. The line space of the circuit layer of the first middle density wiring structure is greater than a line space of a circuit layer of the high density wiring structure.

公开(公告)号：US20240290515A1

公开(公告)日：2024-08-29

申请号：US18114181

申请日：2023-02-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wu Chou HSU ,  Hung Yi CHUANG ,  Shin-Luh TARNG

IPC: H01B1/20 ,  H05K1/02 ,  H05K1/11 ,  H05K5/00

CPC classification number: H01B1/20 ,  H05K1/0233 ,  H05K1/115 ,  H05K5/0026

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes an electronic component and a first connection element. The electronic component includes a conductive wire and a magnetic layer encapsulating the conductive wire. The first connection element is electrically connected to the conductive wire. The first connection element is disposed outside the magnetic layer.

公开(公告)号：US20210288024A1

公开(公告)日：2021-09-16

申请号：US17322764

申请日：2021-05-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Meng-Kai SHIH ,  Teck-Chong LEE ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US20210202349A1

公开(公告)日：2021-07-01

申请号：US16730400

申请日：2019-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsin-En CHEN ,  Hung-Hsien HUANG ,  Shin-Luh TARNG

IPC: H01L23/373 ,  H01L23/498

Abstract: A semiconductor device package includes a semiconductor die and an anisotropic thermal conductive structure. The semiconductor die includes a first surface, a second surface opposite to the first surface and edges connecting the first surface to the second surface. The anisotropic thermal conductive structure has different thermal conductivities in different directions. The anisotropic thermal conductive structure includes at least two pairs of film stacks, and each pair of the film stacks comprises a metal film and a nano-structural film alternately stacked. The anisotropic thermal conductive structure comprises a first thermal conductive section disposed on the first surface of the semiconductor die, and the first thermal conductive section is wider than the semiconductor die.

公开(公告)号：US20190244909A1

公开(公告)日：2019-08-08

申请号：US15891305

申请日：2018-02-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yong-Da CHIU ,  Shiu-Chih WANG ,  Shang-Kun HUANG ,  Ying-Ta CHIU ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L23/532 ,  H01L23/00

CPC classification number: H01L23/53233 ,  H01L23/53238 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/161 ,  H05K2201/03 ,  H05K2201/09481

Abstract: A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.

公开(公告)号：US20220243992A1

公开(公告)日：2022-08-04

申请号：US17163217

申请日：2021-01-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hung-Hsien HUANG ,  Shin-Luh TARNG ,  Ian HU ,  Chien-Neng LIAO ,  Jui-Cheng YU ,  Po-Cheng HUANG

IPC: F28D15/04 ,  F28D15/02 ,  F28F13/18

Abstract: A heat transfer element, a method for manufacturing the same and a semiconductor structure including the same are provided. The heat transfer element includes a housing, a chamber, a dendritic layer and a working fluid. The chamber is defined by the housing. The dendritic layer is disposed on an inner surface of the housing. The working fluid is located within the chamber.

公开(公告)号：US20220056589A1

公开(公告)日：2022-02-24

申请号：US17000239

申请日：2020-08-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Wei CHIANG ,  Shin-Luh TARNG ,  Chih-Pin HUNG ,  Shiu-Chih WANG ,  Yong-Da CHIU

IPC: C23C18/16 ,  H01L21/67 ,  H01L21/768

Abstract: An electroless semiconductor bonding structure, an electroless plating system and an electroless plating method of the same are provided. The electroless semiconductor bonding structure includes a first substrate and a second substrate. The first substrate includes a first metal bonding structure disposed adjacent to a first surface of the first substrate. The second substrate includes a second metal bonding structure disposed adjacent to a second surface of the second substrate. The first metal bonding structure connects to the second metal bonding structure at an interface by electroless bonding and the interface is substantially void free.