FENCE MANAGEMENT OVER MULTIPLE BUSSES
    31.
    发明申请
    FENCE MANAGEMENT OVER MULTIPLE BUSSES 有权
    多个总线的财务管理

    公开(公告)号:US20150149673A1

    公开(公告)日:2015-05-28

    申请号:US14089237

    申请日:2013-11-25

    Applicant: Apple Inc.

    CPC classification number: G06F13/405 G06F13/362 G06F13/364 G06F13/4027

    Abstract: Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command.

    Abstract translation: 公开了桥单元和系统的实施例,其可以允许处理围栏命令发送到多个桥单元。 每个桥单元可以处理由主单元生成的多个交易的相应部分。 主单元可以被配置为向每个桥单元发送fence命令,这可能阻止命令的处理。 每个桥单元可以被配置为确定包括在其多个事务的相应部分中的所有事务是否已经完成。 一旦每个桥接单元已经确定所有其他桥接单元已经接收到围栏命令,并且所有其他桥接单元已经完成了在接收到围栏命令之前接收到的多个事务的各自部分,则所有桥单元可以执行fence命令 。

    Edge-triggered interrupt conversion in a system employing level-sensitive interrupts
    32.
    发明授权
    Edge-triggered interrupt conversion in a system employing level-sensitive interrupts 有权
    采用级别敏感中断的系统中的边沿触发中断转换

    公开(公告)号:US09009377B2

    公开(公告)日:2015-04-14

    申请号:US13666132

    申请日:2012-11-01

    Applicant: Apple Inc.

    CPC classification number: G06F13/24

    Abstract: In an embodiment, a system includes an interrupt controller, one or more CPUs coupled to the interrupt controller, a communication fabric, one or more peripheral devices configured to generate interrupts to be transmitted to the interrupt controller, and one or more interrupt message circuits coupled to the peripheral devices. The interrupt message circuits are configured to generate interrupt messages to convey the interrupts over the fabric to the interrupt controller. Some of the interrupts are level-sensitive interrupts, and the interrupt message circuits are configured to transmit level-sensitive interrupt messages to the interrupt controller. At least one of the interrupts is edge-triggered. The system is configured to convert the edge-triggered interrupt to a level-sensitive interrupt so that interrupts may be handled in the same fashion.

    Abstract translation: 在一个实施例中,系统包括中断控制器,耦合到中断控制器的一个或多个CPU,通信结构,被配置为产生要发送到中断控制器的中断的一个或多个外围设备,以及一个或多个中断消息电路耦合 到外围设备。 中断消息电路被配置为产生中断消息,以将中断通过结构传送到中断控制器。 一些中断是电平敏感中断,并且中断消息电路被配置为向中断控制器发送电平敏感中断消息。 至少有一个中断是边沿触发的。 该系统配置为将边沿触发中断转换为电平敏感中断,以便可以以相同的方式处理中断。

    PROTOCOL CONVERSION INVOLVING MULTIPLE VIRTUAL CHANNELS
    33.
    发明申请
    PROTOCOL CONVERSION INVOLVING MULTIPLE VIRTUAL CHANNELS 有权
    涉及多个虚拟通道的协议转换

    公开(公告)号:US20140304441A1

    公开(公告)日:2014-10-09

    申请号:US13859000

    申请日:2013-04-09

    Applicant: APPLE INC.

    CPC classification number: G06F13/385

    Abstract: Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels.

    Abstract translation: 公开了桥接电路和系统的实施例,其可以允许将事务从一个通信协议转换到另一个通信协议。 桥接电路可以耦合到采用第一通信协议的第一总线,以及采用第二通信协议的第二总线。 第二总线可以包括多个虚拟通道。 桥接电路可以被配置为通过第一总线接收事务,并将事务转换为第二通信协议,并将转换的事务分配给多个虚拟通道中的一个。 可以进一步配置桥接电路来存储转换的事务。 取决于多个虚拟信道的可用信用数量,桥电路可以产生多个有限吞吐量信号。

    BRIDGE CIRCUIT FOR BUS PROTOCOL CONVERSION AND ERROR HANDLING
    34.
    发明申请
    BRIDGE CIRCUIT FOR BUS PROTOCOL CONVERSION AND ERROR HANDLING 有权
    用于总线协议转换和错误处理的桥接电路

    公开(公告)号:US20140223049A1

    公开(公告)日:2014-08-07

    申请号:US13760795

    申请日:2013-02-06

    Applicant: APPLE INC.

    CPC classification number: G06F13/4027 G06F11/0766 G06F11/0772

    Abstract: Embodiments of a bridge circuit and system are disclosed that may allow for converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The bridge circuit may be configured to convert transactions from the first communication protocol to the second communication protocol, and convert transaction from the second communication protocol to the first communication protocol. In one embodiment, the bridge circuit may be further configured to flag transactions that cannot be converted from the second communication protocol to the first communication protocol. In a further embodiment, an error circuit coupled to the bridge circuit may be configured to detect flagged transactions.

    Abstract translation: 公开了桥接电路和系统的实施例,其可以允许将事务从一个通信协议转换到另一个通信协议。 桥接电路可以耦合到采用第一通信协议的第一总线,以及采用第二通信协议的第二总线。 桥接电路可以被配置为将事务从第一通信协议转换为第二通信协议,并将事务从第二通信协议转换为第一通信协议。 在一个实施例中,桥接电路可以被进一步配置为标记不能从第二通信协议转换到第一通信协议的事务。 在另一个实施例中,耦合到桥接电路的错误电路可以被配置为检测标记的事务。

    Bridge circuit reorder buffer for transaction modification and translation
    35.
    发明授权
    Bridge circuit reorder buffer for transaction modification and translation 有权
    桥接电路重排序缓冲器用于事务修改和翻译

    公开(公告)号:US08793411B1

    公开(公告)日:2014-07-29

    申请号:US13785983

    申请日:2013-03-05

    Applicant: Apple Inc.

    CPC classification number: G06F13/4027 G06F13/28

    Abstract: Embodiments of a bridge circuit and system are disclosed that may allow for converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The bridge circuit may be configured to receive transactions over the first bus and store parameters associated with the received transactions. The bridge circuit may be further configured to modify the received transaction, convert the modified transaction to the second communication protocol, and transmit the converted transaction over the second bus.

    Abstract translation: 公开了桥接电路和系统的实施例,其可以允许将事务从一个通信协议转换到另一个通信协议。 桥接电路可以耦合到采用第一通信协议的第一总线,以及采用第二通信协议的第二总线。 桥接电路可以被配置为通过第一总线接收事务并存储与所接收的事务相关联的参数。 桥接电路还可以被配置为修改接收到的事务,将修改后的事务转换为第二通信协议,并通过第二总线发送转换的事务。

    Debug registers for halting processor cores after reset or power off
    36.
    发明授权
    Debug registers for halting processor cores after reset or power off 有权
    调试寄存器用于在复位或关闭电源后暂停处理器内核

    公开(公告)号:US08694830B2

    公开(公告)日:2014-04-08

    申请号:US13765920

    申请日:2013-02-13

    Applicant: Apple Inc.

    CPC classification number: G06F11/26 G06F11/3656

    Abstract: A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

    Abstract translation: 公开了一种停止用于调试目的的集成电路(IC)的功能块的方法和装置。 在一个实施例中,IC包括可由外部调试器经由调试端口(DP)访问的多个功能单元。 在调试操作期间,IC中的电源控制器可以关闭功能单元。 当功能单元关闭电源时,可以对第一个寄存器进行编程。 响应于第一寄存器的编程,第一信号可以被断言并提供给功能单元。 当功能恢复到功能单元时,可以在执行指令或其他操作之前响应于该信号来停止功能单元的操作。

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