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    CHROMA CACHE ARCHITECTURE IN BLOCK PROCESSING PIPELINES
    2.
    发明申请
    CHROMA CACHE ARCHITECTURE IN BLOCK PROCESSING PIPELINES 有权
    块式加工管道中的色谱高速缓存架构

    公开(公告)号：US20160065973A1

    公开(公告)日：2016-03-03

    申请号：US14472119

    申请日：2014-08-28

    Applicant: APPLE INC.

    Inventor： Guy Cote ,  Joseph P. Bratt ,  Timothy J. Millet ,  Shing I. Kong ,  Joseph J. Cheng

    IPC: H04N19/186 ,  H04N19/423 ,  H04N19/172 ,  H04N19/176

    CPC classification number: H04N19/186 ,  G06F12/00 ,  G06F12/0207 ,  G06F12/0862 ,  G06F12/121 ,  G06F2212/1024 ,  G06F2212/455 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06T1/60 ,  H04N19/127 ,  H04N19/172 ,  H04N19/176 ,  H04N19/423 ,  H04N19/433 ,  H04N19/439

    Abstract: Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued.

    Abstract translation: 在块处理流水线中缓存参考数据的方法和装置。 可以实现缓存，其可以从存储器预取哪个对应于在流水线中处理的块的运动矢量的参考数据。 可以在处理阶段之前一个或多个阶段启动用于运动矢量的预取。 高速缓存的缓存标签可以由运动向量定义。 当接收到运动矢量时，可以检查标签以确定是否存在与缓存中的向量（高速缓存命中）相对应的高速缓存块。 在缓存未命中时，根据替换策略来选择高速缓存中的高速缓存块，相应的标签被更新，并且发出用于各个参考数据的预取（例如，经由DMA）。

    SYSTEMS AND METHODS FOR LOCAL TONE MAPPING
    3.
    发明申请
    SYSTEMS AND METHODS FOR LOCAL TONE MAPPING 有权
    用于局部色调映射的系统和方法

    公开(公告)号：US20150348246A1

    公开(公告)日：2015-12-03

    申请号：US14822316

    申请日：2015-08-10

    Applicant: APPLE INC.

    Inventor： Suk Hwan Lim ,  D. Amnon Silverstein ,  Guy Cote ,  Steven David Hordley ,  Graham Finlayson ,  Weichun Ku ,  Joseph P. Bratt

    IPC: G06T5/00 ,  G06T1/20 ,  G06K9/38 ,  G06T5/50

    CPC classification number: G06T5/001 ,  G06K9/38 ,  G06T1/20 ,  G06T5/002 ,  G06T5/003 ,  G06T5/008 ,  G06T5/50 ,  G06T2207/10024 ,  G06T2207/20012 ,  G06T2207/20028 ,  G06T2207/20208

    Abstract: Systems and methods for local tone mapping are provided. In one example, an electronic device includes an electronic display, an imaging device, and an image signal processor. The electronic display may display images of a first bit depth, and the imaging device may include an image sensor that obtains image data of a higher bit depth than the first bit depth. The image signal processor may process the image data, and may include local tone mapping logic that may apply a spatially varying local tone curve to a pixel of the image data to preserve local contrast when displayed on the display. The local tone mapping logic may smooth the local tone curve applied to the intensity difference between the pixel and another nearby pixel exceeds a threshold.

    Abstract translation: 提供了本地色调映射的系统和方法。 在一个示例中，电子设备包括电子显示器，成像设备和图像信号处理器。 电子显示器可以显示第一位深度的图像，并且成像装置可以包括获得比第一位深度更高的位深度的图像数据的图像传感器。 图像信号处理器可以处理图像数据，并且可以包括本地色调映射逻辑，其可以将空间上变化的本地色调曲线应用于图像数据的像素，以便在显示器上显示时保持局部对比度。 本地色调映射逻辑可以平滑应用于像素和另一附近像素之间的强度差超过阈值的局部色调曲线。

    CLOCK CONTROL FOR DMA BUSSES
    4.
    发明申请
    CLOCK CONTROL FOR DMA BUSSES 有权

    公开(公告)号：US20150278134A1

    公开(公告)日：2015-10-01

    申请号：US14709336

    申请日：2015-05-11

    Applicant: Apple Inc.

    Inventor： David G. Conroy ,  Timothy J. Millet ,  Joseph P. Bratt

    IPC: G06F13/34 ,  G06F13/16

    CPC classification number: G06F13/34 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/28 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/171

    Abstract: A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer.

    DATA STORAGE AND ACCESS IN BLOCK PROCESSING PIPELINES
    5.
    发明申请
    DATA STORAGE AND ACCESS IN BLOCK PROCESSING PIPELINES 有权
    数据存储和访问块处理管道

    公开(公告)号：US20150092843A1

    公开(公告)日：2015-04-02

    申请号：US14039764

    申请日：2013-09-27

    Applicant: Apple Inc.

    Inventor： Timothy John Millet ,  Mark P. Rygh ,  Craig M. Okruhlica ,  Jim C. Chou ,  Guy Cote ,  Gaurav S. Gulati ,  Joseph J. Cheng ,  Joseph P. Bratt

    IPC: H04N19/57 ,  H04N19/186 ,  H04N19/182

    CPC classification number: H04N19/423 ,  H04N19/53

    Abstract: Block processing pipeline methods and apparatus in which reference data are stored to a memory according to tile formats to reduce memory accesses when fetching the data from the memory. When the pipeline stores reference data from a current frame being processed to memory as a reference frame, the reference samples are stored in macroblock sequential order. Each macroblock sample set is stored as a tile. Reference data may be stored in tile formats for luma and chroma. Chroma reference data may be stored in tile formats for chroma 4:2:0, 4:2:2, and/or 4:4:4 formats. A stage of the pipeline may write luma and chroma reference data for macroblocks to memory according to one or more of the macroblock tile formats in a modified knight's order. The stage may delay writing the reference data from the macroblocks until the macroblocks have been fully processed by the pipeline.

    Abstract translation: 块处理管道方法和装置，其中参考数据根据瓦片格式存储到存储器中，以在从存储器取出数据时减少存储器访问。 当流水线将正在处理的当前帧的参考数据存储为参考帧时，参考样本以宏块顺序存储。 每个宏块样本集被存储为一个图块。 参考数据可以以瓦片和色度的瓦片格式存储。 色度参考数据可以以瓦4：2：0,4：2：2和/或4：4：4格式的瓦片格式存储。 流水线的一个阶段可以根据改进的骑士顺序中的一个或多个宏块瓦片格式将宏块的亮度和色度参考数据写入存储器。 该阶段可以延迟从宏块写入参考数据，直到宏块已被管道完全处理。

    Data storage and access in block processing pipelines
    7.
    发明授权
    Data storage and access in block processing pipelines 有权
    块处理管道中的数据存储和访问

    公开(公告)号：US09571846B2

    公开(公告)日：2017-02-14

    申请号：US14039764

    申请日：2013-09-27

    Applicant: Apple Inc.

    Inventor： Timothy John Millet ,  Mark P. Rygh ,  Craig M. Okruhlica ,  Jim C. Chou ,  Guy Cote ,  Gaurav S. Gulati ,  Joseph J. Cheng ,  Joseph P. Bratt

    IPC: H04N19/423 ,  H04N19/56 ,  H04N19/53

    CPC classification number: H04N19/423 ,  H04N19/53

    Abstract: Block processing pipeline methods and apparatus in which reference data are stored to a memory according to tile formats to reduce memory accesses when fetching the data from the memory. When the pipeline stores reference data from a current frame being processed to memory as a reference frame, the reference samples are stored in macroblock sequential order. Each macroblock sample set is stored as a tile. Reference data may be stored in tile formats for luma and chroma. Chroma reference data may be stored in tile formats for chroma 4:2:0, 4:2:2, and/or 4:4:4 formats. A stage of the pipeline may write luma and chroma reference data for macroblocks to memory according to one or more of the macroblock tile formats in a modified knight's order. The stage may delay writing the reference data from the macroblocks until the macroblocks have been fully processed by the pipeline.

    Abstract translation: 块处理管道方法和装置，其中参考数据根据瓦片格式存储到存储器中，以在从存储器取出数据时减少存储器访问。 当流水线将正在处理的当前帧的参考数据存储为参考帧时，参考样本以宏块顺序存储。 每个宏块样本集被存储为一个图块。 参考数据可以以瓦片和色度的瓦片格式存储。 色度参考数据可以以瓦4：2：0,4：2：2和/或4：4：4格式的瓦片格式存储。 流水线的一个阶段可以根据改进的骑士顺序中的一个或多个宏块瓦片格式将宏块的亮度和色度参考数据写入存储器。 该阶段可以延迟从宏块写入参考数据，直到宏块已被管道完全处理。

    Buffer underrun handling
    8.
    发明授权
    Buffer underrun handling 有权
    缓冲区欠载处理

    公开(公告)号：US09336563B2

    公开(公告)日：2016-05-10

    申请号：US14163326

    申请日：2014-01-24

    Applicant: Apple Inc.

    Inventor： Joseph P. Bratt ,  Peter F. Holland ,  Shing Horng Choo ,  Timothy J. Millet ,  Brijesh Tripathi

    IPC: G09G5/39 ,  G06T1/60

    CPC classification number: G06T1/60 ,  G09G5/39

    Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.

    Abstract translation: 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。

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