公开(公告)号：US09367474B2

公开(公告)日：2016-06-14

申请号：US13915911

申请日：2013-06-12

Applicant: Apple Inc.

Inventor： Shailendra S. Desai ,  Gurjeet S. Saund ,  Deniz Balkan ,  James Wang

IPC: G06F12/0893 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0893 ,  G06F12/0802 ,  G06F12/0888 ,  G06F12/12 ,  Y02D10/13

Abstract: Systems and methods for translating cache hints between different protocols within a SoC. A requesting agent within the SoC generates a first cache hint for a transaction, and the first cache hint is compliant with a first protocol. The first cache hint can be set to a reserved encoding value as defined by the first protocol. Prior to the transaction being sent to the memory subsystem, the first cache hint is translated into a second cache hint. The memory subsystem recognizes cache hints which are compliant with a second protocol, and the second cache hint is compliant with the second protocol.

Abstract translation: 用于翻译SoC中不同协议之间的缓存提示的系统和方法。 SoC中的请求代理生成用于事务的第一高速缓存提示，并且第一高速缓存提示符合第一协议。 第一个缓存提示可以设置为第一个协议定义的保留编码值。 在将事务发送到存储器子系统之前，第一高速缓存提示被转换成第二高速缓存提示。 存储器子系统识别符合第二协议的高速缓存提示，并且第二高速缓存提示符合第二协议。

公开(公告)号：US09270610B2

公开(公告)日：2016-02-23

申请号：US13778482

申请日：2013-02-27

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Gurjeet S Saund ,  Kevin C Wong ,  Munetoshi Fukami

IPC: H04L12/865 ,  H04L12/863 ,  H04W28/10

CPC classification number: H04L47/6275 ,  H04L47/6205 ,  H04L47/6295 ,  H04W28/10

Abstract: Various embodiments of a method and apparatus for controlling transaction flow in a communications fabric is disclosed. In one embodiment, an IC includes a communications fabric connecting multiple agents to one another. Each agent may include an interface coupling itself to at least one other agent. Each interface may include multiple queues for storing information corresponding to pending transactions. Also included in each interface is an arbitration unit and control logic. The control logic may determine which transactions are presented to the arbitration unit for arbitration. In one embodiment, the control logic may inhibit certain transactions from being presented to the arbitration unit so that other higher priority transactions may advance. In another embodiment, the control logic may reduce the priority level of some transactions for arbitration purposes to prevent the blocking of other higher priority transactions.

Abstract translation: 公开了用于控制通信结构中的事务流的方法和装置的各种实施例。 在一个实施例中，IC包括将多个代理彼此连接的通信结构。 每个代理可以包括将自身耦合到至少一个其他代理的接口。 每个接口可以包括用于存储对应于待处理事务的信息的多个队列。 每个接口中还包括一个仲裁单元和控制逻辑。 控制逻辑可以确定哪些事务被呈现给仲裁单元进行仲裁。 在一个实施例中，控制逻辑可以禁止某些交易被呈现给仲裁单元，使得其他更高优先级的事务可以提前。 在另一个实施例中，控制逻辑可以减少用于仲裁目的的一些交易的优先级，以防止阻塞其他更高优先级的事务。

公开(公告)号：US20130159775A1

公开(公告)日：2013-06-20

申请号：US13765920

申请日：2013-02-13

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Kevin R. Walker ,  Mitchell P. Lichtenberg

IPC: G06F11/26

CPC classification number: G06F11/26 ,  G06F11/3656

Abstract: A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

Abstract translation: 公开了一种停止用于调试目的的集成电路（IC）的功能块的方法和装置。 在一个实施例中，IC包括可由外部调试器经由调试端口（DP）访问的多个功能单元。 在调试操作期间，IC中的电源控制器可以关闭功能单元。 当功能单元关闭电源时，可以对第一个寄存器进行编程。 响应于第一寄存器的编程，第一信号可以被断言并提供给功能单元。 当功能恢复到功能单元时，可以在执行指令或其他操作之前响应于该信号来停止功能单元的操作。

公开(公告)号：US20200050379A1

公开(公告)日：2020-02-13

申请号：US16059766

申请日：2018-08-09

Applicant: Apple Inc.

Inventor： Nachiappan Chidambaram Nachiappan ,  David L. Trawick ,  Yiu Chun Tse ,  Deniz Balkan ,  Hengsheng Geng ,  Shawn Munetoshi Fukami ,  Jaideep Dastidar ,  Benjamin K. Dodge ,  Vinodh R. Cuppu

IPC: G06F3/06 ,  G06F13/16 ,  H04W72/04 ,  H04L12/853 ,  H04W28/02

Abstract: A system and method for efficiently allocating data storage to agents. A computing system includes an interconnect with intermediate buffers for storing transactions and corresponding payload data during transport between sources and destinations. A data storage limit is set on an amount of data storage corresponding to outstanding transactions for each of the multiple sources based on the initial buffer assignments. A number of outstanding transactions for each of the multiple sources is limited based on a corresponding data storage limit. If the rate of allocation of a given buffer assigned to a first source exceeds a threshold, then a second source is selected with available space exceeding a threshold in an assigned buffer. If it is determined the second source is not assigned to a buffer with a rate of allocation exceeding a threshold, then buffer storage is reassigned from the second source to the first source.

公开(公告)号：US10324865B2

公开(公告)日：2019-06-18

申请号：US15257527

申请日：2016-09-06

Applicant: Apple Inc.

Inventor： Deniz Balkan

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric are disclosed. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge allows writes to pass reads for a given source, but prevents reads from passing writes. The bridge forwards a write transaction out of the bridge when the write transaction is available for forwarding. The bridge forwards a read transaction from a given source out of the bridge when there are no outstanding write transactions for the given source that are older than the read transaction. The bridge prevents forwarding the read transaction from the given source out of the bridge when there are outstanding write transactions that are older than the read transaction for the given source.

公开(公告)号：US20160359476A1

公开(公告)日：2016-12-08

申请号：US14730473

申请日：2015-06-04

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Jean-Didier Allegrucci ,  Timothy Paaske ,  Deniz Balkan

IPC: H03K5/19 ,  H03K5/26

CPC classification number: H03K5/19 ,  H03K5/26

Abstract: An apparatus may include first and second clock monitors. The first clock monitor may be configured to receive a first clock signal and assert a first signal if the frequency of the first clock signal is greater than a first upper threshold and assert a second signal if the frequency of the first clock signal is less than a first lower threshold. The second clock monitor may be configured to receive a second clock signal with a frequency higher than that of the first clock signal. The second clock monitor may be configured to compare the second clock signal, dependent upon the first clock signal, to second upper and lower thresholds and assert a third signal if the frequency of the second clock signal is greater than the second upper threshold and assert a fourth signal if the frequency is less than the second lower threshold.

Abstract translation: 装置可以包括第一和第二时钟监视器。 如果第一时钟信号的频率大于第一上限阈值，则第一时钟监视器可以被配置为接收第一时钟信号并且断言第一信号，并且如果第一时钟信号的频率小于第一时钟信号，则断言第二信号 第一个下限 第二时钟监视器可以被配置为接收频率高于第一时钟信号的频率的第二时钟信号。 第二时钟监视器可被配置为根据第一时钟信号将第二时钟信号与第二上限和下限阈值进行比较，并且如果第二时钟信号的频率大于第二上限阈值则断言第三信号，并且断言第 第四信号，如果频率小于第二较低阈值。

公开(公告)号：US09189435B2

公开(公告)日：2015-11-17

申请号：US13868313

申请日：2013-04-23

Applicant: Apple Inc.

Inventor： Benjamin K. Dodge ,  Deniz Balkan ,  Gurjeet S. Saund ,  Munetoshi Fukami

IPC: G06F13/16 ,  G06F13/368

CPC classification number: G06F13/368 ,  G06F13/16

Abstract: A method and apparatus for arbitration. In one embodiment, a point in a network includes first and second arbiters. Arbitration of transactions associated with an address within a first range are conducted in the first arbiter, while arbitration of transactions associated with an address within a second range are conducted in the second arbiter. Each transaction is one of a number of different transaction types having a respective priority level. A measurement circuit is coupled to receive information from the first and second arbiters each cycle indicating the type of transactions that won their respective arbitrations. The measurement circuit may update a number of credits associated with the types of winning transactions. The updated number of credits may be provided to both the first and second arbiters, and may be used as a basis for arbitration in the next cycle.

Abstract translation: 一种用于仲裁的方法和装置。 在一个实施例中，网络中的一个点包括第一和第二仲裁器。 与第一范围内的地址相关联的交易的仲裁在第一仲裁器中进行，而与第二范围内的地址相关联的交易的仲裁在第二仲裁器中进行。 每个事务是具有相应优先级的多个不同事务类型之一。 耦合测量电路以从第一和第二仲裁器接收信息，每个周期指示赢得其各自仲裁的交易类型。 测量电路可以更新与获胜交易的类型相关联的多个信用。 可以将更新的信用数量提供给第一和第二仲裁器，并且可以用作下一周期中的仲裁的基础。

公开(公告)号：US09135202B2

公开(公告)日：2015-09-15

申请号：US13760795

申请日：2013-02-06

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Shu-Yi Yu

IPC: G06F13/40 ,  G06F11/07

CPC classification number: G06F13/4027 ,  G06F11/0766 ,  G06F11/0772

Abstract: Embodiments of a bridge circuit and system are disclosed that may allow for converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The bridge circuit may be configured to convert transactions from the first communication protocol to the second communication protocol, and convert transaction from the second communication protocol to the first communication protocol. In one embodiment, the bridge circuit may be further configured to flag transactions that cannot be converted from the second communication protocol to the first communication protocol. In a further embodiment, an error circuit coupled to the bridge circuit may be configured to detect flagged transactions.

Abstract translation: 公开了桥接电路和系统的实施例，其可以允许将事务从一个通信协议转换到另一个通信协议。 桥接电路可以耦合到采用第一通信协议的第一总线，以及采用第二通信协议的第二总线。 桥接电路可以被配置为将事务从第一通信协议转换为第二通信协议，并将事务从第二通信协议转换为第一通信协议。 在一个实施例中，桥接电路可以被进一步配置为标记不能从第二通信协议转换到第一通信协议的事务。 在另一个实施例中，耦合到桥接电路的错误电路可以被配置为检测标记的事务。

公开(公告)号：US20140181349A1

公开(公告)日：2014-06-26

申请号：US13724886

申请日：2012-12-21

Applicant: APPLE INC.

Inventor： Deniz Balkan ,  Gurjeet S. Saund

IPC: G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/4059 ,  G06F2213/0038

Abstract: Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge maintains a pair of counters for each source in a SoC to track the numbers of outstanding read and write transactions. The bridge prevents a read transaction from being forwarded to the second bus if the corresponding write counter is non-zero, and the bridge prevents a write transaction from being forwarded to the second bus if the corresponding read counter is non-zero.

Abstract translation: 用于通过总线结构中的桥梁维护每个源的读取和写入事务顺序的系统和方法。 该桥提供从总线结构中的第一总线到第二总线的连接。 第一个总线具有读取和写入事务的单一路径，第二个总线具有用于读取和写入事务的独立路径。 该桥在SoC中为每个源保留一对计数器，以跟踪未完成的读写事务的数量。 如果相应的写计数器不为零，桥将阻止读事务被转发到第二总线，如果相应的读计数器不为零，桥将阻止写事务被转发到第二总线。

公开(公告)号：US20140122759A1

公开(公告)日：2014-05-01

申请号：US13666132

申请日：2012-11-01

Applicant: APPLE INC.

Inventor： Erik P. Machnicki ,  Deniz Balkan ,  Manu Gulati

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: In an embodiment, a system includes an interrupt controller, one or more CPUs coupled to the interrupt controller, a communication fabric, one or more peripheral devices configured to generate interrupts to be transmitted to the interrupt controller, and one or more interrupt message circuits coupled to the peripheral devices. The interrupt message circuits are configured to generate interrupt messages to convey the interrupts over the fabric to the interrupt controller. Some of the interrupts are level-sensitive interrupts, and the interrupt message circuits are configured to transmit level-sensitive interrupt messages to the interrupt controller. At least one of the interrupts is edge-triggered. The system is configured to convert the edge-triggered interrupt to a level-sensitive interrupt so that interrupts may be handled in the same fashion.

Abstract translation: 在一个实施例中，系统包括中断控制器，耦合到中断控制器的一个或多个CPU，通信结构，被配置为产生要发送到中断控制器的中断的一个或多个外围设备，以及一个或多个中断消息电路耦合 到外围设备。 中断消息电路被配置为产生中断消息，以将中断通过结构传送到中断控制器。 一些中断是电平敏感中断，并且中断消息电路被配置为向中断控制器发送电平敏感中断消息。 至少有一个中断是边沿触发的。 该系统配置为将边沿触发中断转换为电平敏感中断，以便可以以相同的方式处理中断。