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    STANDALONE FLOATING-POINT CONVERSION UNIT
    33.
    发明申请
    STANDALONE FLOATING-POINT CONVERSION UNIT 有权
    STANDALONE浮点转换单元

    公开(公告)号：US20160092169A1

    公开(公告)日：2016-03-31

    申请号：US14498172

    申请日：2014-09-26

    申请人： ARM Limited

    发明人： David Raymond LUTZ ,  Neil BURGESS

    IPC分类号： G06F7/485 ,  G06F5/01

    CPC分类号： G06F7/485

    摘要： A data processing apparatus includes floating-point adder circuitry and floating-point conversion circuitry that generates a floating-point number as an output by performing a conversion on any input having a format from a list of formats including: an integer number, a fixed-point number, and a floating-point number having a format smaller than the output floating-point number. The floating-point conversion circuitry is physically distinct from the floating-point adder circuitry.

    摘要翻译： 数据处理装置包括浮点加法器电路和浮点转换电路，其通过对从格式列表格式的任何输入执行转换来产生浮点数，该格式包括：整数， 点数，以及格式小于输出浮点数的浮点数。 浮点转换电路在物理上不同于浮点加法器电路。

    APPARATUS AND METHOD FOR EFFICIENT DIVISION PERFORMANCE
    34.
    发明申请
    APPARATUS AND METHOD FOR EFFICIENT DIVISION PERFORMANCE 有权
    装置和方法，用于有效的部门性能

    公开(公告)号：US20150378681A1

    公开(公告)日：2015-12-31

    申请号：US14315940

    申请日：2014-06-26

    申请人： ARM Limited

    发明人： Neil BURGESS ,  David Raymond LUTZ

    IPC分类号： G06F7/535 ,  G06F5/01

    CPC分类号： G06F7/535 ,  G06F5/01 ,  G06F7/537 ,  G06F9/3001

    摘要： A data processing apparatus and method of operating such a data processing apparatus are provided, for responding to a division instruction to perform a division operation to generate a result value by dividing an input numerator specified by the division instruction by an input denominator specified by the division instruction. The input numerator and input denominator are binary values. The apparatus comprises division circuitry configured to generate the result value by carrying out the division operation, power-of-two detection circuitry configured to signal a bypass condition if the input denominator has a value given by ±2N, where N is a positive integer, and bypass circuitry configured, in response to signalling of the bypass condition, to cause the division circuitry to be bypassed and to cause the result value to be generated as the input numerator shifted by N bits.

    摘要翻译： 提供了一种操作这种数据处理装置的数据处理装置和方法，用于响应分割指令执行除法运算，以通过将由除法指令指定的输入分子除以由分割器指定的输入分母来产生结果值 指令。 输入分子和输入分母是二进制值。 该装置包括分配电路，其被配置为通过执行除法运算来产生结果值，二次检测电路被配置为在输入分母具有由±2N给出的值时发出旁路条件，其中N是正整数， 以及旁路电路，响应于旁路条件的信号，配置为使旁路分路电路，并且使输出分子移位N位时产生结果值。

    DATA PROCESSING APPARATUS AND METHOD FOR MULTIPLYING FLOATING POINT OPERANDS
    35.
    发明申请
    DATA PROCESSING APPARATUS AND METHOD FOR MULTIPLYING FLOATING POINT OPERANDS 有权
    数据处理装置和浮动点操作的方法

    公开(公告)号：US20150254066A1

    公开(公告)日：2015-09-10

    申请号：US14200923

    申请日：2014-03-07

    申请人： ARM Limited

    发明人： David Raymond LUTZ ,  Neil Burgess

    IPC分类号： G06F7/487 ,  G06F5/01

    CPC分类号： G06F7/4876 ,  G06F5/012 ,  G06F7/49952 ,  G06F7/49957 ,  G06F7/5336 ,  G06F2207/483

    摘要： A data processing apparatus and method are provided for multiplying first and second normalised floating point operands in order to generate a result, each normalised floating point operand comprising a significand and an exponent. Exponent determination circuitry is used to compute a result exponent for a normalised version of the result, and rounding value generation circuitry then generates a rounding value by shifting a rounding constant in a first direction by a shift amount that is dependent on the result exponent. Partial product generation circuitry multiplies the significands of the first and second normalised floating point operands to generate the first and second partial products, and the first and second partial products are then added together, along with the rounding value, in order to generate a normalised result significand. Thereafter, the normalised result significand is shifted in a second direction opposite to the first direction, by the shift amount, in order to generate a rounded result significand. This provides a particularly efficient mechanism for multiplying floating point numbers, whilst correctly rounding the result in situations where the result is subnormal.

    摘要翻译： 提供了一种数据处理装置和方法，用于对第一和第二标准化浮点操作数进行乘法，以便产生结果，每个归一化浮点操作数包括有效位数和指数。 指数确定电路用于计算结果的归一化版本的结果指数，并且舍入值生成电路然后通过将第一方向上的舍入常数移位取决于结果指数的移位量来生成舍入值。 部分产品生成电路将第一和第二标准化浮点运算数的有效数乘以生成第一和第二部分乘积，然后将第一和第二部分乘积与舍入值一起加在一起，以便生成归一化结果 有意义 此后，归一化结果有效位置在与第一方向相反的第二方向上移位移位量，以产生舍入结果有效。 这提供了一种用于乘以浮点数的特别有效的机制，同时在结果为异常的情况下正确地舍入结果。

    COMPARING A RUNLENGTH OF BITS WITH A VARIABLE NUMBER
    36.
    发明申请
    COMPARING A RUNLENGTH OF BITS WITH A VARIABLE NUMBER 审中-公开
    比较具有可变数量的位的运行

    公开(公告)号：US20150227346A1

    公开(公告)日：2015-08-13

    申请号：US14606217

    申请日：2015-01-27

    申请人： ARM LIMITED

    发明人： Neil BURGESS ,  David Raymond LUTZ

    IPC分类号： G06F7/74

    CPC分类号： G06F7/74 ,  G06F7/764

    摘要： Processing circuitry 2 is provided for comparing a number of adjacent widths having a common value and extending from a starting position within an input number with a runlength specified by a variable number. The circuitry includes a mask generator 22 for generating a mask value in dependence upon the variable number, combination circuitry 24 for performing a logical combination operation upon respective bits within the input number starting from the starting position and corresponding bits within the mask value so as to generate an intermediate value. Result circuitry 26 then generates a result indicative of whether or not the number of adjacent bits is less than or equal to the run length in dependence upon a determination if any bits within the intermediate value have a predetermined value.

    摘要翻译： 处理电路2被提供用于比较具有公共值的多个相邻宽度并且从输入号码内的开始位置延伸到由可变数量指定的游程长度。 该电路包括掩模发生器22，用于根据可变数产生掩模值，组合电路24用于对从开始位置开始的输入数字内的各个位和掩模值内的对应位执行逻辑组合操作，以便 生成中间值。 结果电路26然后根据确定中间值中的任何位是否具有预定值，生成指示相邻位的数量是否小于或等于游程长度的结果。

    DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A NARROWING-AND-ROUNDING ARITHMETIC OPERATION
    37.
    发明申请
    DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A NARROWING-AND-ROUNDING ARITHMETIC OPERATION 有权
    数据处理装置及其实现简单的算术运算方法

    公开(公告)号：US20150039665A1

    公开(公告)日：2015-02-05

    申请号：US13955324

    申请日：2013-07-31

    申请人： Arm Limited

    发明人： Neil BURGESS ,  David Raymond LUTZ

    IPC分类号： G06F7/499

    CPC分类号： G06F7/49947 ,  G06F7/50 ,  G06F7/506

    摘要： A processing apparatus supports a narrowing-and-rounding arithmetic operation which generates, in response to two operands each comprising at least one W-bit data element, a result value comprising at least one X-bit result data element, with each X-bit result data element representing a sum or difference of corresponding W-bit data elements of the two operands rounded to an X-bit value (W>X). The arithmetic operation is implemented using a number of N-bit additions (N

    摘要翻译： 一种处理装置支持缩小和舍入的算术运算，其响应于每个包括至少一个W位数据元素的两个操作数产生包括至少一个X位结果数据元素的结果值，每个X位 结果数据元素表示舍入到X位值（W> X）的两个操作数的相应W位数据元素的和或差。 使用多个N位加法（N

    TININESS DETECTION
    39.
    发明申请
    TININESS DETECTION 有权

    公开(公告)号：US20230035159A1

    公开(公告)日：2023-02-02

    申请号：US17384001

    申请日：2021-07-23

    申请人： Arm Limited

    发明人： David Raymond LUTZ ,  David M. RUSSINOFF ,  Harsha VALSARAJU

    IPC分类号： G06F7/483 ,  G06F7/499 ,  G06F7/10 ,  G06F5/01

    摘要： An apparatus comprises floating-point processing circuitry to perform a floating-point operation with rounding to generate a floating-point result value; and tininess detection circuitry to detect a tininess status indicating whether an outcome of the floating-point operation is tiny. A tiny outcome corresponds to a non-zero number with a magnitude smaller than a minimum non-zero magnitude representable as a normal floating-point number in a floating-point format to be used for the floating-point result value. The tininess detection circuitry comprises hardware circuit logic configured to support both before rounding tininess detection and after rounding tininess detection for detecting the tininess status.

    FLOATING-POINT SCALING OPERATION
    40.
    发明申请
    FLOATING-POINT SCALING OPERATION 审中-公开

    公开(公告)号：US20200371805A1

    公开(公告)日：2020-11-26

    申请号：US16416453

    申请日：2019-05-20

    申请人： Arm Limited

    发明人： David Raymond LUTZ

    IPC分类号： G06F9/30

    摘要： An apparatus has floating-point multiplying circuitry to perform a floating-point multiply operation to multiply first and second floating-point operands to generate a product floating-point value. Shared hardware circuitry of the floating-point multiplying circuitry is reused to also support a floating-point scaling instruction specifying an input floating-point operand and an integer operand, which causes a floating-point scaling operation to be performed to generate an output floating-point value corresponding to a product of the input floating-point operand and a scaling factor 2X, where X is an integer represented by the integer operand.