公开(公告)号：US20200099406A1

公开(公告)日：2020-03-26

申请号：US16140364

申请日：2018-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Balwinder Singh ,  Milam Paraschou ,  Chad S. Gallun ,  Jeffrey Cooper ,  Dean E. Gonzales ,  Alushulla Jack Ambundo ,  Thomas H. Likens, III ,  Gerald R. Talbot

IPC: H04B1/04 ,  H04B1/16 ,  H01L27/02 ,  H03M1/80

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

公开(公告)号：US20250007516A1

公开(公告)日：2025-01-02

申请号：US18763572

申请日：2024-07-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Kumar ,  Edoardo Prete ,  Gerald R. Talbot ,  Ethan Crain ,  Tracy J. Feist ,  Jeffrey Cooper

IPC: H03K19/0175 ,  H03F3/45

Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.

公开(公告)号：US11960435B2

公开(公告)日：2024-04-16

申请号：US17692147

申请日：2022-03-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Pradeep Jayaraman ,  Dean Gonzales ,  Gerald R. Talbot ,  Ramon A. Mangaser ,  Michael J. Tresidder ,  Prasant Kumar Vallur ,  Srikanth Reddy Gruddanti ,  Krishna Reddy Mudimela Venkata ,  David H. McIntyre

IPC: G06F13/42 ,  H01L25/065

CPC classification number: G06F13/4291 ,  G06F13/4286 ,  H01L25/0652

Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

公开(公告)号：US20190181087A1

公开(公告)日：2019-06-13

申请号：US15836239

申请日：2017-12-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Sanjay Dandia ,  Gerald R. Talbot ,  Mahesh S. Hardikar

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: An integrated circuit assembly includes an integrated circuit package substrate and a conductive land pad disposed on a surface of the integrated circuit package substrate. The conductive land pad comprises a conductor portion, an isolated conductor portion, and an isolation portion disposed between the conductor portion and the isolated conductor portion. The isolated conductor portion may surround a first side of the conductor portion and a second side of the conductor portion. The isolated conductor portion may surround a portion of a perimeter of the conductor portion. The isolation portion may include a gap between the conductor portion and the isolated conductor portion. The gap may have a width smaller than a radius of an interconnect structure of a receiving structure.

公开(公告)号：US09374080B2

公开(公告)日：2016-06-21

申请号：US14518591

申请日：2014-10-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brian W. Amick ,  Gerald R. Talbot ,  Warren Anderson

IPC: H03K17/22

CPC classification number: H03K17/22

Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.

Abstract translation: 提供一种方法和装置，用于在上电期间输出复位信号，直到满足两个条件。 在一个实施例中，所述方法和装置包括电压检测器，当调节器的输出电压（“VREG”）超过阈值电压时提供第一输出（“VO1”），从而满足第一条件，比较器接收第一 输入电压和第二输入电压，当第一输入电压超过第二输入电压时，比较器提供第二输出（“VO2”），从而满足第二条件，以及释放电路，输出复位信号，除非电压检测器提供 VO1，而比较器提供VO2。