公开(公告)号：US11791245B2

公开(公告)日：2023-10-17

申请号：US17395215

申请日：2021-08-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt ,  Kay Stefan Essig

IPC: H01L23/495 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L23/3107 ,  H01L23/4952 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06548

Abstract: An electronic package includes a patterned conductive layer and at least one conductive protrusion on the patterned conductive layer. The at least one conductive protrusion has a first top surface. The patterned conductive layer and the at least one conductive protrusion define a space. The electronic package further includes a first electronic component disposed in the space and a plurality of conductive pillars on the first electronic component. The conductive pillars have a second top surface. The first top surface is substantially level with the second top surface.

公开(公告)号：US20230046889A1

公开(公告)日：2023-02-16

申请号：US17402239

申请日：2021-08-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl Appelt

IPC: H01L23/498 ,  H01L21/48

Abstract: An electronic carrier and a method of manufacturing an electronic carrier are provided. The electronic carrier includes a first interconnection structure and a second interconnection structure. The first interconnection structure includes a first patterned conductive layer having a first pattern density. The second interconnection structure is laminated to the first interconnection structure and includes a second patterned conductive layer having a second pattern density higher than the first pattern density. The first interconnection structure is electrically coupled to the second interconnection structure through a first non-soldering joint between and outside of the first interconnection structure and the second interconnection structure.

公开(公告)号：US11574856B2

公开(公告)日：2023-02-07

申请号：US17221597

申请日：2021-04-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl Appelt ,  You-Lung Yen ,  Kay Stefan Essig

IPC: H01L23/49 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.

公开(公告)号：US11322454B2

公开(公告)日：2022-05-03

申请号：US16717948

申请日：2019-12-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device package includes an electronic component, an infrared blocking layer, an upper protection layer and a side protection layer. The infrared blocking layer includes a first portion disposed over the electronic component. The infrared blocking layer includes a second portion surrounding the electronic component. The first portion is integral with the second portion. The upper protection layer is disposed on the first portion of the infrared blocking layer. The side protection layer is disposed on the second portion of the infrared blocking layer. The upper protection layer and the side protection layer are formed of different materials.

公开(公告)号：US10777478B2

公开(公告)日：2020-09-15

申请号：US15649543

申请日：2017-07-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl Appelt ,  Kay Stefan Essig

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065 ,  H01L21/768 ,  H01L23/367 ,  H01L23/48 ,  H01L23/14

Abstract: A semiconductor package device includes a first die having a first surface and a second surface opposite to the first surface, and a first adhesive layer disposed on the first surface of the first die. The semiconductor package device further includes an encapsulant layer encapsulating the first die and the first adhesive layer, and a first conductive via disposed in the first adhesive layer and electrically connected to the first die.

公开(公告)号：US10186467B2

公开(公告)日：2019-01-22

申请号：US15649545

申请日：2017-07-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl Appelt ,  Kay Stefan Essig ,  Chi-Tsung Chiu

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/48 ,  H01L23/14

Abstract: A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

公开(公告)号：US09196597B2

公开(公告)日：2015-11-24

申请号：US14453139

申请日：2014-08-06

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/28

CPC classification number: H01L24/14 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/49155 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

Abstract translation: 多层衬底包括第一外部导电图案化层，暴露第一外部导电图案化层的一部分以限定第一组焊盘的第一绝缘层，第二外部导电图案化层和暴露部分第一绝缘层的第二绝缘层 第二外导电图案层以限定第二组焊盘。 多层基板还包括内层，每层具有内部导电图案层，邻近内部导电图案化层形成的多个内部导电柱和内部电介质层，其中内部导电图案层和内部导电柱嵌入内部 电介质层和每个内部导电柱的顶表面从内部电介质层露出。