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49 条记录 (耗时 0.045 秒)

    FLASH MEMORY
    31.
    发明申请
    FLASH MEMORY 有权
    闪存

    公开(公告)号：US20130140621A1

    公开(公告)日：2013-06-06

    申请号：US13308959

    申请日：2011-12-01

    申请人： Albert Chin ,  Chun-Yang Tsai

    发明人： Albert Chin ,  Chun-Yang Tsai

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/513 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

    摘要： A MONOS Charge-Trapping flash (CTF), with record thinnest 3.6 nm ENT trapping layer, has a large 3.1V 10-year extrapolated retention window at 125° C. and excellent 106 endurance at a fast 100 is and ±16 V program/erase. This is achieved using As+-implanted higher κ trapping layer with deep 5.1 eV work-function of As. In contrast, the un-implanted device only has a small 10-year retention window of 1.9 V at 125° C. A MoN—[SiO2—LaAlO3]—[Ge—HfON]—[LaAlO3—SiO2]—Si CTF device is also provided with record-thinnest 2.5-nm Equivalent-Si3N4-Thickness (ENT) trapping layer, large 4.4 V initial memory window, 3.2 V 10-year extrapolated retention window at 125° C., and 3.6 V endurance window at 106 cycles, under very fast 100 μs and low ±16 V program/erase. These were achieved using Ge reaction with HfON trapping layer for better charge-trapping and retention.

    摘要翻译： 具有记录最薄的3.6nm ENT捕获层的MONOS电荷俘获闪光（CTF）在125℃下具有大的3.1V 10年外推保留窗口，并且在快速100和±16V程序/ 擦除 这是使用As + - 具有深度5.1 eV功能的As的高+ kappa陷阱层实现的。 相比之下，未植入的装置在125℃仅具有1.9V的小的10年保留窗口.MN- [SiO 2 -AlAl 3/3] - [Ge-HfON] - [LaAlO 3 -Si 2] -Si CTF装置是 还提供了记录最薄的2.5纳米等效Si3N4厚度（ENT）捕获层，大4.4 V初始记忆窗口，125°C下3.2 V 10年外推保留窗口，以及106个循环的3.6 V耐力窗口， 在非常快的100 mus和低±16 V程序/擦除。 这些是通过与HfON捕获层的Ge反应来实现的，以更好的电荷捕获和保留。

    Method for making very low Vt metal-gate/high-κ CMOSFETs using self-aligned low temperature shallow junctions
    32.
    发明授权
    Method for making very low Vt metal-gate/high-κ CMOSFETs using self-aligned low temperature shallow junctions 有权
    制造非常低的Vt金属栅极/高压晶体管的方法 CMOSFET采用自对准低温浅结

    公开(公告)号：US07754551B2

    公开(公告)日：2010-07-13

    申请号：US12216561

    申请日：2008-07-08

    申请人： Albert Chin

    发明人： Albert Chin

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/338 ,  H01L21/22 ,  H01L21/38

    CPC分类号： H01L21/823814 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

    摘要： This invention proposes a method for making very low threshold voltage (Vt) metal-gate/high-κ CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EOT), good effective work-function of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85° C. bias-temperature-instability

    摘要翻译： 本发明提出了一种制造极低阈值电压（Vt）金属栅极/高电平的方法。 CMOSFET采用新型自对准低温超浅结，具有与VLSI兼容的栅极优先处理。 在1.2nm等效氧化物厚度（EOT）下，5.3和4.1eV的良好有效功函数，+0.05和0.03V的低Vt，90和243cm 2 / Vs的高迁移率和小于85℃的偏置温度 测量p和n-MOS的稳定性<32mV（10MV / cm，1小时）。

    Method for making low Vt gate-first light-reflective-layer covered dual metal-gates on high-k CMOSFETs
    33.
    发明申请
    Method for making low Vt gate-first light-reflective-layer covered dual metal-gates on high-k CMOSFETs 审中-公开
    在高k CMOSFET上制造低Vt栅极 - 第一光反射层覆盖双金属栅极的方法

    公开(公告)号：US20090263944A1

    公开(公告)日：2009-10-22

    申请号：US12081518

    申请日：2008-04-17

    申请人： Albert Chin

    发明人： Albert Chin

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517

    摘要： This invention proposes a method for making low Vt light-reflective-layer/dual-metal-gates/high-κ CMOSFETs with simple light-irradiation anneal and light-reflective-layer covered dual metal-gates with self-aligned and gate-first process compatible with current VLSI process. At 1.05 nm EOT, good φm-eff of 5.04 and 4.24 eV, low Vt of −0.16 and 0.13 V, high mobility of 85 and 209 cm2/Vs, and small 85° C. BTI≦40 mV (10 MV/cm, 1 hr) were measured for p- and n-MOSFETs. Using novel very high-κ TiLaO gate dielectric, low Vt of −0.07 and 0.12 V and high mobility of 82 and 203 cm2/Vs were achieved even at small EOT of 0.63 nm.

    摘要翻译： 本发明提出了一种利用简单的光照射退火制造低Vt光反射层/双金属栅极/高kappa CMOSFET的方法，其具有自对准和栅极优先的具有光反射层的双金属栅极 过程与当前的VLSI过程兼容。 在1.05nm EOT下，5.04和4.24eV的良好的phim-eff，-0.16和0.13V的低Vt，85和209cm2 / Vs的高迁移率，以及小于85℃.BTI <= 40mV（10MV / cm ，1小时）测量p和n-MOSFET。 使用新型非常高kappa TiLaO栅极电介质，即使在0.63nm的小EOT下也获得了低Vt为-0.07和0.12V，高迁移率为82和203cm2 / Vs。

    ASYMMETRIC-LDD MOS DEVICE
    34.
    发明申请
    ASYMMETRIC-LDD MOS DEVICE 审中-公开
    不对称LDD MOS器件

    公开(公告)号：US20090090980A1

    公开(公告)日：2009-04-09

    申请号：US11868546

    申请日：2007-10-08

    申请人： Mingchu King ,  Albert Chin

    发明人： Mingchu King ,  Albert Chin

    IPC分类号： H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

    CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66659

    摘要： The present invention proposes a new asymmetric-lightly-doped drain (LDD) metal oxide semiconductor (MOS) transistor that is fully embedded in a CMOS logic. The radio frequency (RF) power performance of both conventional and asymmetric MOS transistor is measured and compared. The output power can be improved by 38% at peak power-added efficiency (PAE). The PAE is also improved by 16% at 10-dBm output power and 2.4 GHz. These significant improvements of RF power performance by this new MOS transistor make the RF-CMOS system-on-chip design a step further. Index Terms—Lightly-doped-drain (LDD), metal oxide semiconductor field effect transistor (MOSFET), metal oxide semiconductor (MOS) transistor, radio frequency (RF) power transistor.

    摘要翻译： 本发明提出了完全嵌入在CMOS逻辑中的新的非对称轻掺杂漏极（LDD）金属氧化物半导体（MOS）晶体管。 测量和比较常规和非对称MOS晶体管的射频（RF）功率性能。 在峰值功率附加效率（PAE）下，输出功率可以提高38％。 在10 dBm输出功率和2.4 GHz时，PAE也提高了16％。 这种新型MOS晶体管的RF功率性能的显着改进使RF-CMOS片上系统的设计进一步发展。 索引术语 - 轻掺杂漏极（LDD），金属氧化物半导体场效应晶体管（MOSFET），金属氧化物半导体（MOS）晶体管，射频（RF）功率晶体管。

    Cardiac electrode attachment procedure
    35.
    发明申请
    Cardiac electrode attachment procedure 审中-公开
    心电极贴附程序

    公开(公告)号：US20060116746A1

    公开(公告)日：2006-06-01

    申请号：US11326933

    申请日：2006-01-05

    申请人： Albert Chin

    发明人： Albert Chin

    IPC分类号： A61N1/05

    CPC分类号： A61B17/3468 ,  A61B2017/00243 ,  A61N1/0587 ,  A61N2001/0578

    摘要： Surgical procedure and surgical instruments include an electrode structure for insertion through tissue superiorly of a subxiphoid incision to a position posterior of an aspect of the sternum and anterior of the pericardium. The electrode structure may be expanded, for example, including an inflatable member to position a number of electrodes of the electrode structure in contact with the pericardium. Alternatively, an electrode structure on an insertion cannula may be retained in contact with the pericardium by the cannula positioned within the dissected tissue. Electrical conductors from the contacting electrodes are routed through the tract of dissected tissue toward the subxiphoid incision for attachment to a generator that is implanted in a subcutaneous pocket near the subxiphoid incision.

    摘要翻译： 外科手术和手术器械包括用于插入通过下棘切口上方的组织到胸骨一侧位置和心包前方的位置的电极结构。 电极结构可以被膨胀，例如包括可膨胀构件以将电极结构的多个电极定位成与心包接触。 或者，插入插管上的电极结构可以通过位于解剖组织内的套管保持与心包接触。 来自接触电极的电导体通过解剖组织的路径被引导到副棘齿切口，以附着到植入在副下棘切口附近的皮下袋中的发生器上。

    Resistive random access memory (RRAM) using stacked dielectrics and method for manufacturing the same
    39.
    发明授权
    Resistive random access memory (RRAM) using stacked dielectrics and method for manufacturing the same 有权
    使用堆叠电介质的电阻随机存取存储器（RRAM）及其制造方法

    公开(公告)号：US08791444B2

    公开(公告)日：2014-07-29

    申请号：US13304085

    申请日：2011-11-23

    申请人： Albert Chin ,  Chun-Hu Cheng

    发明人： Albert Chin ,  Chun-Hu Cheng

    IPC分类号： H01L47/00

    CPC分类号： H01L45/04 ,  B82Y10/00 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

    摘要： Resistive random access memory (RRAM) using stacked dielectrics and a method for manufacturing the same are disclosed, where a setting power of only 4 μW, an ultra-low reset power of 2 nW, good switching uniformity and excellent cycling endurance up to 5×109 cycles were achieved simultaneously. Such record high performances were reached in a Ni/GeOx/nano-crystal-TiO2/TaON/TaN RRAM device, where the excellent endurance is 4˜6 orders of magnitude larger than existing Flash memory. The very long endurance and low switching energy RRAM is not only satisfactory for portable SSD in a computer, but may also create new applications such as being used for a Data Center to replace high power consumption hard discs.

    摘要翻译： 公开了使用堆叠电介质的电阻随机存取存储器（RRAM）及其制造方法，其中设置功率仅为4μW，超低复位功率为2nW，良好的开关均匀性和优异的循环耐受性高达5× 同时实现了109个循环。 在Ni / GeOx /纳米晶体TiO2 / TaON / TaN RRAM器件中达到了这样的高性能，其耐久性比现有闪存大4〜6个数量级。 非常长的耐用性和低开关能量RRAM不仅对于计算机中的便携式SSD是令人满意的，而且还可以创建新的应用，例如用于数据中心来替代高功率硬盘。